Problem 4. You are trying to select pulldowns for several 3- and 4-input CMOS gate designs. The Pulldowns-R-Us website offers seven different pulldowns, given names PD1 through PD7, diagrammed below:...

Extracted text: Problem 4. You are trying to select pulldowns for several 3- and 4-input CMOS gate designs. The Pulldowns-R-Us website offers seven different pulldowns, given names PD1 through PD7, diagrammed below: PD1 PD2 PD3 PD4 PD5 PD6 PD7 The web site explains that the customer can choose which inputs or constants (GND, VDD) are connected to each NFET, allowing their pulldowns to be used in various ways to build gates with various numbers of inputs. Since Pulldowns-R-Us charges by transistor, you are interested in selecting pulldowns using the minimum number of transistors for each of the 3-input gates you are designing. For each of the following 3- and 4-input Boolean functions, choose the appropriate pulldown design, i.e., the one which, properly connected, implements that gate's pulldown using the minimum number of transistors. This may require applying Demorgan's Laws or minimizing the logic equation first. If none of the above pulldowns meets this goal, write "N (A) F(A,B,C)= A+(B.C) Choice or NONE: (B) F(A,B,C) = A+B•C Choice or NONE: (C) F(A,B,C) = (A B)+C Choice or NONE: (D) F(A,B,C,D) = A+C (B+D) Choice or NONE: 6.004 Worksheet - 4 of 10 - Combinational Logic