Please use CodeWarrior to write an assembly program to do the followings:
- Turn on only LED0 and LED7 continuously during the normal operation.
- Turn on all LEDs whenever there is XIRQ interrupt.
- Go back to normal operation after no more interrupt.
- This process continues until a Reset.
Assembly Program You will have 45 minutes to complete this part of the exam. You may use your textbook for this part of the Final Exam. Instructions: This is similar to the IRQ interrupt example program in the Unit 5 Lecture 8. Please use CodeWarrior to write an assembly program to do the followings: · Turn on only LED0 and LED7 continuously during the normal operation. · Turn on all LEDs whenever there is XIRQ interrupt. · Go back to normal operation after no more interrupt. · This process continues until a Reset. Suggestions: · You should type in the example program on IRQ interrupt that is in the Unit 5 Lecture 8, assemble it, download it, and test it. Understand this example program completely by reading the Unit 5 Lecture 8, on IRQ and by testing the example program. · Then, read Unit 5 Lecture 8 slides on XIRQ interrupt, and modify the main: delete the code for enabling low-level triggering and for enabling IRQ pin, and add code to enable XIRQ pin, and clear the X bit (bit 6) in CCR. · Change the service routine name from IRQ_ISR to XIRQ_ISR; Set up interrupt vector for XIRQ_ISR (Please understand how IRQ_ISR is set up in the example program, and do it similarly to set up XIRQ_ISR using the XIRQ interrupt vector), After you have successfully assembled your program, and debugged your program, download your program, and test your program. Notes: PAGE Eet430 Microcontrollers EET430 Microcontrollers Lecture 8 HCS12’s Interrupts, and Its Assembly Programming Dr. Ning Hu ECPI University Outline HCS12’s Interrupt concept HCS12’s Interrupt Vector Table Mask(Disable)/Enable Interrupts Globally Enable/Disable an Interrupt locally External Hardware/Internal Hardware Interrupts HCS12 Interrupt Priority HCS12 Interrupt Programming Programming HCS12 Timer Systems by Interrupts Lab 8 21/17/2017 1:04 PM The Goal of the Course 1. To understand Microcontroller in general, and HCS12 in particular 2. To be able to program the HCS12 Microcontrollers to control external devices 31/17/2017 1:04 PM How to Achieve the Goal? Must learn the following: 1. Hardware of the Microcontrollers: Memory maps, CPU registers, and I/O ports 2. Software of the Microcontrollers: Addressing modes, and Instruction Set 3. Programming skills: Sequences, loops, and branches (IF – ELSE) 4. Tools: CodeWarrior 41/17/2017 1:04 PM What is An Interrupt? An event that causes the CPU to suspend whatever it is doing, and to handle this event. Such an event is called an interrupt. Interrupts can occur at any time, because the events that cause interrupts can happen at any time. 51/17/2017 1:04 PM Interrupt Service Routines (ISR) The way that a CPU handles an interrupt is by executing a special program that is written jus for this interrupt. Such a special program is called Interrupt Service Routine (ISR) or Interrupt handler. An interrupt service routine (ISR) is not a simple subroutine. An interrupt service routine (ISR) differs from a subroutine in that it is pre-coded and stored in specified locations of the Memory. The last instruction in an ISR is RTI (not RTS). 61/17/2017 1:04 PM Interrupt Vectors For every interrupt, a fixed two-byte memory location is reserved for it. This reserved two-byte memory location is called its interrupt vector; For example, the interrupt vector for Reset is the last two bytes $FFFE, $FFFF, or vector ($FFFE, $FFFF). The two bytes in an interrupt vector are used to hold the starting address of the associated interrupt service routines. 71/17/2017 1:04 PM Interrupt Vector Table HCS12 microcontrollers set aside a block of memory to host all the interrupt vectors. This block of memory is called the interrupt vector table; An interrupt vector table is typically in a EEPROM. 81/17/2017 1:04 PM HCS12 Interrupt Vector Table 9 Partial Listing of Interrupt Vector Table for the HCS12 1/17/2017 1:04 PM Interrupts and CCR 10 The I bit and X bit in the CCR Register 1/17/2017 1:04 PM Resets and Interrupts HCS12’s interrupts can be broadly classified into two categories: 1) Resets; 2) Interrupts; Resets can be regarded as special interrupts; 111/17/2017 1:04 PM HCS12’s Resets There are four resets: 1) Power-on reset; 2) Computer Operating Properly (COP) reset; 3) Clock Monitor reset; 4) External reset (the reset button); 121/17/2017 1:04 PM HCS12’s Interrupts The regular interrupts of HCS12 can be futher divided into following two categories: Software interrupt – HCS12 provides only one software interrupt, called SWI, which is an instruction. Whenever this instruction is executed, the corresponding ISR at location $$FFF6 and FFF7 is executed; Hardware interrupts – Except SWI, all the other regular interrupts are classified as hardware interrupts (more details on next slide); 131/17/2017 1:04 PM HCS12’s Hardware Interrupts External hardware interrupts - two pins associated with such hardware interrupts: IRQ and XIRQ. Invalid instruction exception (trap) - an exception interrupt, invoked internally when there are conditions a CPU is unable to handle, such as invalid opcode. Peripheral interrupts – occurs as the result of a condition set by a peripheral module such as HCS12’s timer system or HCS12’s analog-to-digital converter module. The majority of HCS12’s interrupts belongs to Peripheral interrupts category. 141/17/2017 1:04 PM Maskable Interrupts An Interrupt is called maskable interrupt if it can be masked out (disabled) by setting a specific bit. Such an maskable interrupt can also be unmasked (enabled) by clear this bit; Most of the HCS12’s interrupts are maskable. Someone suddenly open your door is an interrupt. You can mask out such an interrupt by locking the door from inside. Or, you can enable such interrupt by unlocking the door from inside. 151/17/2017 1:04 PM Mask/Enable Interrupts Globally Most of the HCS12’s interrupts are maskable as a group – meaning they can be disabled as a group: This group is called maskable group; To mask the entire group, set (SEI) the I bit in CCR; To enable/un-mask the entire group, clear (CLI) the I bit in CCR. 161/17/2017 1:04 PM Enable/disable an individual Interrupt Most of HCS12;s interrupts can also be enabled/disabled individually by setting or clearing its local enable bit; If I bit in CCR is cleared, then, set the local enable bit for an interrupt will enable the interrupt, and clear this bit will disable this interrupt; If I bit in CCR is set, then, the entire maskable group is disabled regardless the status of the local bits for each individual interrupt. 171/17/2017 1:04 PM Steps In Handling An Interrupt HCS12 will follow following steps when handling an interrupt: Upon receiving an interrupt signal, the CPU will 1. suspend the execution of the current program; 2. push all the CPU registers onto Stack; 3. Jump to and execute the associated interrupt service routine(ISR); 4. after CPU executing the last instruction in ISR, which is RTI, it will restore the CPU registers; 5. resume the execution of the suspended program. These steps only apply to regular interrupts, not apply to resets. 181/17/2017 1:04 PM HCS12 CPU Register Stacking Order 191/17/2017 1:04 PM External Hardware Interrupt: IRQ 201/17/2017 1:04 PM External Hardware Interrupt: IRQ IRQ interrupt vector: ($FFF2, $FFF3) ; Pin PE1of PORTE is used to send an IRQ input signal; IRQ is part of the group of the maskable interrupts that can be enabled/disabled globally by the I bit of the CCR. To enable IRQ globally, use instruction CLI To mask out (disable) IRQ, use instruction SEI To use IRQ, it must also be enabled locally; 211/17/2017 1:04 PM External Hardware Interrupt: IRQ (cont.) IRQ can be triggered by either an active-low level or by a high-to-low falling-edge; We must configure INTCR register to enable IRQ locally, and to choose triggering mode. 22 Interrupt Control Register: INTCR 1/17/2017 1:04 PM External Hardware Interrupt: IRQ (cont.) Level-triggered IRQ - In the level-triggered mode, the IRQ pin is normally high, and if a low-level signal is applied to it, it triggers the interrupt. The IRQ pin must be brought back to high by the time RTI is executed. Using level-triggered interrupt allows us to tie together interrupts from several sources & feed it to the IRQ pin. 231/17/2017 1:04 PM External Hardware Interrupt: IRQ (cont.) Edge-triggered IRQ - IRQE bit in the INTCR determines if IRQ is triggered by an active-low level or a falling-edge. Instruction: BSET INTCR, %10000000 makes IRQ an falling-edge triggered interrupt. assuming that the I bit in the CCR register is cleared; a high-to-low signal applied to pin PE1 will interrupt the controller and force it to use its interrupt vector ($FFF2, $FFF3) to jump to its ISR; 241/17/2017 1:04 PM An Example of IRQ Interrupt Programming Please write an assembly program to do the followings: Turn on only LED0 and LED7 continuously during the normal operation; Turn on all LEDs whenever there is a active-low IRQ interrupt; Go back to normal operation after no more interrupt; This process continues until a Reset. 251/17/2017 1:04 PM The Screen Shot of the Example Program: The Main Program 261/17/2017 1:04 PM The Screen Shot of the Example Program: The IRQ Interrupt Service Routine 271/17/2017 1:04 PM External Hardware Interrupt: XIRQ 281/17/2017 1:04 PM External Hardware Interrupt: XIRQ XIRQ interrupt vector: ($FFF4, $FFF5); Pin PE0 of PORTE is used to send an input signal for XIRQ interrupt; After enabling the XIRQ (X bit = 0 in CCR), it cannot be disabled; Thus, it is also called non-maskable interrupt; The only way to disabled it again is to reset the controller; XIRQ is triggered only by an active-low level. 291/17/2017 1:04 PM External Hardware Interrupt: XIRQ (cont.) To enable and use XIRQ, X-bit in CCR must be cleared. To clear X-bit: ANDCC #$BF Note 1: $BF = %10111111. The above code logically AND CCR with $BF, which clears X (bit 6 in CCR). Note2: XIRQ is non-maskable. So, unlike IRQ, CLI and SEI have no effect on XIRQ. Note3: Unlike IRQ, no need to configure any registers when using XIRQ. Can you write a program for XIRQ similar to the example program for IRQ? 301/17/2017 1:04 PM Other External Hardware Interrupts In addition to IRQ and XIRQ external hardware interrupts, HCS12 microcontrollers also allow us to use PTH (port