Please do all the Pre lab, lab, and post lab.Material: 74LS163 (1), 74LS194 (1), 74LS74 (1), logic gates as needed, LEDs / resistors (6), switches / buttons (2)
Please draw the circuit schematic for the lab
ECE2300L_Lab5 ECE 2300L Lab #5 Spring 2019 Sequential Logic Applications Concepts covered: At the end of this experiment, the student will be able to: • Understand how synchronous counters work. • Understand how shift registers work. • Use a state / transition table to design a simple finite-state machine. • Use timing diagrams to assemble many sequential components together to design a game show circuit. • Learn to write verilog codes for counters and shift registers. Material: 74LS163 (1), 74LS194 (1), 74LS74 (1), logic gates as needed, LEDs / resistors (6), switches / buttons (2) Pre Lab: Many game shows use a circuit to determine which of two or more contestants ring in first. In this lab, we are to design such a circuit with two inputs, S0 and S1, connected to the contestants’ buttons. The circuit has two outputs, Z0 and Z1, connected to LEDs to indicate which contestant rings in first. If Contestant 0 rings in first, LED 0 is turned on and remained on until it is put into a ready state by an external signal (controlled by the game show host or automatically after some time). Similarly, if Contestant 1 rings in first, LED 1 is turned on until the circuit is ready. If there is a tie, both LEDs are turned on until the circuit is ready. To make it more interesting, we’d like to implement a visual “shooting” path built from a row of 4 LEDs that displays the following sequences: • No one rings in: 0000 (reset state, no change) • Contestant 0 rings in first: 0001, 0011, 0111, 1111, 1110, 1100, 1000, 0000 (stop) • Contestant 1 rings in first: 1000, 1100, 1110, 1111, 0111, 0011, 0111, 0000 (stop) • Tie: 1111, 0000, 1111, 0000, 1111, 0000, 1111, 0000 (stop) A. Game Show Finite-State Machine The circuit requires four states: Ready, Win0, Win1, and Tie. One way to map the states to two D flip-flops is to use state 00 for Ready, state 01 for Win0, state 10 for Win1, and state 11 for Tie. With this mapping as shown on the transition table at right, the outputs come directly from the current state and will later used to drive the mode pins of the 74LS194 chip. Note that the transition table to the right DOES NOT include the external signal used to put this finite-state machine to the Ready state. You can add this functionality once you find the next-state logic. 1. Draw the state diagram that reflects the transition table shown above. 2. Use K maps to find the logic expressions of the next-state logic, Q1* and Q0*, as functions of the primary inputs S0 and S1 and the current state Q0 and Q1. 3. Show how you can use the external signal, called “getRdy”, to put the current state to 00, the Ready state. 4. Show the circuit diagram, including the switches/buttons and the LEDs. Present State Q1 Q0 Next State Q1* Q0* S1 S0 = 00 01 10 11 Outputs Z1 Z0 0 0 (Ready) 00 01 10 11 0 0 0 1 (Win0) 01 01 01 01 0 1 1 0 (Win1) 10 10 10 10 1 0 1 1 (Tie) 11 11 11 11 1 1 B. Counter The visual “shooting” path is activated when the game show finite-state machine is in a state other than the Ready state. Since we only need to display a sequence of 8 patterns, we’ll use the 74LS163 chip configured as a mod-8 counter, with the counting sequence 1000, 1001, 1010, 1011, 1100, 1101, 1110, and 1111 before going back to 1000. 1. What is the rationale behind using the above counting sequence instead of other sequences such as 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 0000, … 2. Show the schematic of the 74LS163 configured as the mod-8 counter with the sequence 8, 9, 10, 11, 12, 13, 14, 15, back to 8. C. Shift Register The visual “shooting” path is directly driven by the outputs of the 74LS194 chip. The two mode pins come from the outputs Z0 and Z1 of the game show finite-state machine. Show the schematic of the 74LS194 chip with as few logic gates as possible to create the three patterns for Win0, Win1, and Tie. Lab: A. Draw a block diagram using a computer drawing tool, connect the three main blocks (Finite-State Machine, Counter, Shift Register) and label all the pertinent connections. Provide a reset signal to put the finite-state machine in Ready state, set the counter to 1000, and clear the shooting path (i.e. no LEDs ON upon reset). B. Show the timing diagrams that clearly display how the connecting signals control the functions of the three main blocks. C. Build the whole digital circuitry, using one 74LS74, one 74LS163, one 74LS194, and as few logic chips as possible. Connect a 1Hz clock and verify that all parts of the circuitry work as intended. Then increase the clock frequency to about 10Hz and start to play! Demonstration checked by instructor, date: _________________________ Post Lab: A. Counter with enable and load The verilog code at right provides a basic 4-bit binary counter, with a synchronous reset, rst. 1. The code also includes the following inputs: • ‘en’: When en=1, counting is allowed. When en=0, the counting is frozen. • ‘load’: When load=0, count as usual. When load=1, the counter is loaded with ‘val’. The ‘en’ input takes precedence over ‘load’. Extend the code to include the enable and load features. 2. Write a test bench to verify the counter. Make sure you simulate long enough to see the counter wraps from 15 to 0. Also verify the enable and the load features. 3. Run the simulation and capture the waveform. B. Linear Feedback Shift Register 1. Design a sequential circuit that displays the following 4-bit sequence: 0001, 0010, 0100, 1000, 0011, 0110, 1100, 1011, 0101, 1010, 0111, 1110, 1111, 1101, 1001, back to 0001 a. Show the truth (next state) table. b. Use K maps to simplify the next-state logic expressions. c. Draw the schematic. 2. Write the verilog code for this circuit. 3. Write the test bench to verify this code. 4. Run simulation and capture the waveform. Deliverables: Staple your report in this order Pre Lab — A (all), B (all), C (all) Lab — A (Block Diagram), B (Timing Diagrams) Post Lab — A (all), B (all) module count ( input clk, input rst, input en, input load, input [3:0] val, output reg [3:0] cnt ); always @(posedge clk) begin if (rst) cnt <= 0;="" else="" cnt=""><= cnt + 1; end endmodule cnt="" +="" 1;="" end="">