Optimizing Cache Performance via Advanced Techniques Concepts illustrated by this case study ¦ Nonblocking Caches ¦ Compiler Optimizations for Caches ¦ Software and Hardware Prefetching ¦ Calculating...

Optimizing Cache Performance via Advanced Techniques Concepts illustrated by this case study ¦ Nonblocking Caches ¦ Compiler Optimizations for Caches ¦ Software and Hardware Prefetching ¦ Calculating Impact of Cache Performance on More Complex Processors The transpose of a matrix interchanges its rows and columns; this concept is illustrated here: Here is a simple C loop to show the transpose: for (i = 0; i for (j = 0; j output[j][i] = input[i][j]; } } Assume that both the input and output matrices are stored in the row major order (row major order means that the row index changes fastest). Assume that you are executing a 256_256 double-precision transpose on a processor with a 16 KB fully associative (don’t worry about cache conflicts) least recently used (LRU) replacement L1 data cache with 64-byte blocks. Assume that the L1 cache misses or prefetches require 16 cycles and always hit in the L2 cache, and that the L2 cache can process a request every 2 processor cycles. Assume that each iteration of the preceding inner loop requires 4 cycles if the data are present in the L1 cache. Assume that the cache has a write-allocate fetch-on-write policy for write misses. Unrealistically, assume that writing back dirty cache blocks requires 0 cycles.