Let the pFET of Fig. P3.39 have Vt 5 22 V, k 5 0.25 mA/V2 , and 5 0. (a) If VSS 5 12 V, specify suitable resistances to bias the FET at ID 5 0.5 mA under the following constraints: VS is to be biased...

Let the pFET of Fig. P3.39 have Vt 5 22 V, k 5 0.25 mA/V2 , and 5 0. (a) If VSS 5 12 V, specify suitable resistances to bias the FET at ID 5 0.5 mA under the following constraints: VS is to be biased at (2y3)VSS; VD is to be biased in the middle of the saturation region, and R1 1 R2 $ 3 MV. (b) What happens if in the circuit designed in part (a) we change VSS to 15 V? How is the FET’s operating point affected? (c) Repeat, but with VSS 5 6 V.