Let the FETs of the NAND gate of Fig. P6.60 have Vtn 5 2Vtp 5 0.6 V, kn 5 2.5kp 5 100 A/V2 , and n 5 p 5 0. Assuming that all stray capacitances can be modeled with Ceq 5 1 pF, estimate the...

Let the FETs of the NAND gate of Fig. P6.60 have Vtn 5 2Vtp 5 0.6 V, kn 5 2.5kp 5 100 A/V2 , and n 5 p 5 0. Assuming that all stray capacitances can be modeled with Ceq 5 1 pF, estimate the propagation delays for the following cases: (a) A and B are switched from 0 V to 3 V simultaneously. (b) A is switched from 0 V to 3 V while B is already at 3 V. (c) A and B are switched from 3 V to 0 V simultaneously. (d) B is switched from 3 V to 0 V while A is kept at 3 V. Explain the differences.