L1 cache requires 5 cycles to access and has a miss rate of 5%  L2 cache requires additional 10 cycles to access and has a miss rate of 1%  RAM requires additional 110 cycles to access and has a...

L1 cache requires 5 cycles to access and has a miss rate of 5%

 L2 cache requires additional 10 cycles to access and has a miss rate of 1%
 RAM requires additional 110 cycles to access and has a miss rate of 0%

Calculate the average memory access time based on the above information. Show the details of your working process.