Jitter and Phasor Diagrams We are using a 10 MHz reference signal to clock an analogto-digital converter (ADC). The XXXXXXXXXXMHz reference is contaminated with a second, smaller frequency component...

Jitter and Phasor Diagrams We are using a 10 MHz reference signal to clock an analogto-digital converter (ADC). The 10.000 MHz reference is contaminated with a second, smaller frequency component at 10.001 MHz. The equation of the composite signal s(t) is

a. Draw the phasor diagram using SR(t) as a reference. Show SR(t), SSP(t) and SC(t). You may have to draw the diagram not to scale to show all the components.

b. Using SR(t), the clean, ideal 10.000 MHz oscillator as the reference, find the maximum phase and amplitude deviation of the composite signal SC(t).

c. Examine the zero crossings of SC(t) with respect to those of SR(t). What’s the maximum time difference between the zero crossings of the contaminated reference signal SC(t) and the pure, uncontaminated reference signal SR(t)? In other words, what is the oscillator’s timing jitter?