Integrate the write back cache interface into the sequential DLX design and modify the cost and delay formulae of the memory system. The memory environment and the memory interface control have to be...

Integrate the write back cache interface into the sequential DLX design and modify the cost and delay formulae of the memory system. The memory environment and the memory interface control have to be changed. Note that the FSD of figure 6.27 must be extended by the bus operations.