In the NAND gate of let VDD 5 5 V, and let the FETs be matched devices with Vt 5 1 V, k 5 100 A/V2 , and 5 0. (a) Sketch and label the VTC, and fi nd Vm, NML, and NMH for the case in which A and B are...

In the NAND gate of let VDD 5 5 V, and let the FETs be matched devices with Vt 5 1 V, k 5 100 A/V2 , and 5 0. (a) Sketch and label the VTC, and fi nd Vm, NML, and NMH for the case in which A and B are tied together to confi gure the NAND gate for operation as an inverter. (b) Compare with the basic inverter, and justify the differences. Hint: recall that two identical FETs connected in series act like a single equivalent FET with keq 5 ky2.