In the CS amplifi er of the FET is biased in the diode mode, giving VD 5 VD(EOS) 1 Vt . To allow more headroom for the output signal, it may be desirable to bias the drain somewhat higher, at VD 5...

In the CS amplifi er of the FET is biased in the diode mode, giving VD 5 VD(EOS) 1 Vt . To allow more headroom for the output signal, it may be desirable to bias the drain somewhat higher, at VD 5 VD(EOS) 1 mVt , m . 1. The CS confi guration of achieves this goal by utilizing the additional resistance R2, which forces R1 to drop some voltage, thus raising VD. (a) Show that if R1 and R2 are suffi ciently large to draw negligible current compared to ID, the CS amplifi er of gives, for 5 0,

(b) If VDD 5 5 V and the FET has Vt 5 0.5 V, k 5 2.0 mA/V2 , and  5 0, specify suitable resistances for aoc 5 210 V/V with m 5 2. (c) Recalculate aoc if 5 0.02 V21 , and comment. (d) Verify that your circuit operates properly by showing all node voltages (dc as well as ac component) if vi 5 (100 mV) cos t.