In the CMOS comparator of let k9 n 5 2.5 k9 p 5 120 A/V2 , Vtn 5 2Vtp 5 0.7 V, n 5 p 5 1y(30 V), and L 5 0.75 m. (a) If IREF 5 100 A, specify W1 through W7 for ID6 5 ID7 5 ID8 5 100 A and VOV 5 0.2 V...

In the CMOS comparator of let k9 n 5 2.5 k9 p 5 120 A/V2 , Vtn 5 2Vtp 5 0.7 V, n 5 p 5 1y(30 V), and L 5 0.75 m. (a) If IREF 5 100 A, specify W1 through W7 for ID6 5 ID7 5 ID8 5 100 A and VOV 5 0.2 V throughout. (b) If VDD 5 2VSS 5 2.5 V, specify W9 and W10 so that the total supply current is maximized for vO near 0 V and is 1 mA. (c) What is the overall voltage gain for vO 5 0? Over what output voltage range does this gain hold?