In the CMOS circuit of let VDD 5 2VSS 5 2.5 V, ISS 5 300 A, and RSS 5 `. Also, let the FETs have Vt n 5 2Vtp 5 1.0 V, k9 n 5 2.5 k9 p 5 100 A/ V 2 , n 5 1y[ XXXXXXXXXXV], p 5 1y[ XXXXXXXXXXV]), and n...

In the CMOS circuit of let VDD 5 2VSS 5 2.5 V, ISS 5 300 A, and RSS 5 `. Also, let the FETs have Vt n 5 2Vtp 5 1.0 V, k9 n 5 2.5 k9 p 5 100 A/ V 2 , n 5 1y[(7.5 6 2.5) V], p 5 1y[(22.5 6 4.5) V]), and n 5 0. (a) Using the nominal values of n and p, specify the WpyLp ratio for the M3-M4 pair so that at dc balance the circuit gives VO1 5 VO2 5 0 V. Moreover, specify the WnyLn ratio for the M1-M2 pair so as to achieve VOVn 5 0.5 V. (b) Given the above variabilities of n and p, what is the maximum input offset voltage VOS(max)? Hint: if you assume vI2 5 0, then VOS(max) is the value of vI1 needed to drive vOD to zero under the worst-case mismatch scenario.