In the CMOS circuit of let ISS 5 200 A and RSS 5 `, and let the FETs have kn 5 1 mA/V2 and kp 5 0.1 mA/V2 (for simplicity assume n 5 p 5 0 and n 5 0.) (a) If both kn and kp are affl icted by 65%...

In the CMOS circuit of let ISS 5 200 A and RSS 5 `, and let the FETs have kn 5 1 mA/V2 and kp 5 0.1 mA/V2 (for simplicity assume n 5 p 5 0 and n 5 0.) (a) If both kn and kp are affl icted by 65% tolerances, what is the maximum input offset voltage VOS(max)? Hint: if you assume vI2 5 0, then VOS(max) is the value of vI1 needed to drive vOD to zero under the worst-case mismatch scenario. (b) How are VOS(max) and adm affected if kn is quadrupled, still with the same tolerance as in part (a)? (c) Repeat part (b) but if kp (rather than kn) is now quadrupled, still with 65% tolerances.