In the CMOS circuit of Fig. P4.68 assume matched FETs with Vt n 5 2Vt p 5 1.0 V, kn 5 kp 5 1 mA/V2 , and n 5 p 5 1y(10 V). Estimate the worst-case value of VOS if all three parameter pairs are affl icted by a 65% tolerance. Hint: investigate one half at a time, and then exploit the circuit’s symmetry to generalize.
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