In the class AB output buffer in Fig XXXXXXXXXXor 21.51, a load resistor connected to ground causes the PMOS device to conduct more current then the NMOS. Why? Resituate the buffer in Fig XXXXXXXXXXif...

In the class AB output buffer in Fig. 21.50 or 21.51, a load resistor connected to ground causes the PMOS device to conduct more current then the NMOS. Why? Resituate the buffer in Fig. 21.51 if it drives a 1k resistor and MON is reduced in size to 50/2. Is this a better design? Why or why not?