In the circuit of Fig. P4.47 let VDD 5 2VSS 5 3.5 V, RD1 5 RD2 5 10 kV, ISS 5 0.4 mA, and RSS 5 `. Moreover, let the FETs have k9 5 100 A/V2 , Vt 5 0.6 V, 5 0, and 5 0. (a) Specify the WyL ratio for...

In the circuit of Fig. P4.47 let VDD 5 2VSS 5 3.5 V, RD1 5 RD2 5 10 kV, ISS 5 0.4 mA, and RSS 5 `. Moreover, let the FETs have k9 5 100 A/V2 , Vt 5 0.6 V, 5 0, and 5 0. (a) Specify the WyL ratio for the FETs that will yield vodyvid 5 210 V/V. (b) If vI1 5 vI2 5 0 V, fi nd vO1, vO2, and vS, the voltage at the sources. (c) If the inputs are tied together and are driven by a common voltage vIC, what is the upper limit on vIC for which the FETs are still saturated? (d) What is the vID range needed to steer ISS from one side to the other of the SC pair? Find vO1, vO2, and vS at the extremes of this range.