In the circuit of Fig. P3.78, R biases the FETs at VO 5 VI , and since the FETs are assumed to be matched, we have VO 5 VI 5 VDDy2. (a) Replace the FETs with their small-signal models, and use the...

In the circuit of Fig. P3.78, R biases the FETs at VO 5 VI , and since the FETs are assumed to be matched, we have VO 5 VI 5 VDDy2. (a) Replace the FETs with their small-signal models, and use the test method to obtain expressions for Ri (the input resistance with the output port open-circuited), and Ro (the output resistance with the input port ac shortcircuited) in terms of gm, ro, and R. (b) If R 5 1 MV, Vt 5 1 V, k 5 1 mA/V2 , and 5 0.01 V21 , calculate Ri and Ro for VDD 5 5 V.