In Fig. P3.67, M1 is operated in the CG mode and M2 in the diode mode. By KVL, VS1 5 VGS2 2 VGS1. If we use matched FETs and bias them with identical currents, then VGS1 and VGS2 will cancel each...

In Fig. P3.67, M1 is operated in the CG mode and M2 in the diode mode. By KVL, VS1 5 VGS2 2 VGS1. If we use matched FETs and bias them with identical currents, then VGS1 and VGS2 will cancel each other out, yielding VS1 5 0 V. Since M1’s source is the input node in CG operation, a dc voltage of 0 V is highly desirable there as it allows us to couple the signal source to the amplifi er directly, without the need for any ac-coupling capacitors. Moreover, ac operation extends all the way down to dc, another very desirable feature. In the circuit shown, the CG stage is used as a voltage-tocurrent amplifi er. (a) Let VDD 5 2VSS 5 10 V and RS 5 10 kV. Assuming matched FETs with Vt 5 1.5 V, k 5 2.0 mA/V2 , and 5 0.02 V21 , and assuming the signal source has Rsig 5 10 kV and a dc component of 0 V, specify RB to ensure VS1 5 0. (b) Find the small-signal parameters Ri , Ro, and ioyvsig. How does the gain ioyvsig compare with the ideal case Ri → 0? Hint: after fi nding Ri , fi nd the intermediate voltage gain vi yvsig. (c) What is the maximum voltage that the load can develop and still ensure active-mode operation for M1?