In Chapter 3 we found that connecting a feedback resistance between the output and input terminals of a CMOS inverter will bias it right in the middle of its linear region of operation. In IC...

In Chapter 3 we found that connecting a feedback resistance between the output and input terminals of a CMOS inverter will bias it right in the middle of its linear region of operation. In IC technology resistors are undesirable, so the circuit or Fig. P4.4 utilizes the FET M3 to achieve the same function. Since M1 and M2 draw zero gate currents, M3 operates at the origin of its iD-vDS characteristics, where it acts as a resistance rDS.

(a) Assuming k n 5 2.5k p 5 100 A/ V 2 and Vt n 0 5 2Vt p 0 5 0.5 V, specify WyL ratios for the three devices so that with VDD 5 3 V the inverter is biased at VI 5 VO 5 VDDy2 with rDS 5 1 MV, and it dissipates PD 5 150 W. Since M3 is subject to the body effect, assume 5 0.4 V1y2 and u2 pu 5 0.6 V to fi nd Vt 3.

(b) What happens if due to a wiring error the gate and body terminals of M3 are interchanged with each other, so that the gate goes to ground and the body to VDD? How does PD change? Hint: refer to the nMOSFET structure of Fig. 3.1