In chapter 2, we have introduced a conditional sum adder and a carry look-ahead adder, and extended them to an arithmetical unit AU. In addition to the n-bit sum/difference, the n-bit AU provides two...

In chapter 2, we have introduced a conditional sum adder and a carry look-ahead adder, and extended them to an arithmetical unit AU. In addition to the n-bit sum/difference, the n-bit AU provides two flags indicating an overflow and a negative result. Let DAU n denote the maximal delay of the n-bit AU, and let D_AU
(s[1:0];n denote the delay of the two least significant sum bits.

Show that for both AU designs and for any n ≥ 2 the delay of these two sum bits can be estimated as

 D_AU
(s[1:0];n) D_AU(2).