In a current-steering digital-to-analog converter the current sources suffer from 5 % random mismatch. What DNL can be achieved for a 12-bit unary architecture? How many bits can be implemented in...

In a current-steering digital-to-analog converter the current sources

suffer from 5 % random mismatch. What DNL can be achieved for a 12-bit

unary architecture? How many bits can be implemented in binary format is a

DNL 0:5 LSB must be achieved for 99.7 % of the samples.