im scheduling a test for tomorrow 9 am. having a time limit of 75 minutes, only 1 question about programing TIME LIMITNIS 75 MINUTES. i only have one attempt for this test. running in the program LC-3
app-a “app-a” — 2003/6/30 — page 521 — #1 a p p e n d i x a The LC-3 ISA A.1 Overview The Instruction Set Architecture (ISA) of the LC-3 is defined as follows: Memory address space 16 bits, corresponding to 216 locations, each containing one word (16 bits). Addresses are numbered from 0 (i.e, x0000) to 65,535 (i.e., xFFFF). Addresses are used to identify memory locations and memory-mapped I/O device registers. Certain regions of memory are reserved for special uses, as described in Figure A.1. Bit numbering Bits of all quantities are numbered, from right to left, starting with bit 0. The leftmost bit of the contents of a memory location is bit 15. Instructions Instructions are 16 bits wide. Bits [15:12] specify the opcode (operation to be performed), bits [11:0] provide further information that is x0000 Interrupt Vector Table x01FF x0200 x2FFF x3000 xFDFF xFE00 xFFFF Trap Vector Table Device register addresses Operating system and Supervisor Stack Available for user programs x00FF x0100 Figure A.1 Memory map of the LC-3 “app-a” — 2003/6/30 — page 522 — #2 522 appendix a The LC-3 ISA needed to execute the instruction. The specific operation of each LC-3 instruction is described in Section A.3. Illegal opcode exception Bits [15:12] = 1101 has not been specified. If an instruction contains 1101 in bits [15:12], an illegal opcode exception occurs. Section A.4 explains what happens. Program counter A 16-bit register containing the address of the next instruction to be processed. General purpose registers Eight 16-bit registers, numbered from 000 to 111. Condition codes Three 1-bit registers: N (negative), Z (zero), and P (positive). Load instructions (LD, LDI, LDR, and LEA) and operate instructions (ADD, AND, and NOT) each load a result into one of the eight general purpose registers. The condition codes are set, based on whether that result, taken as a 16-bit 2’s complement integer, is negative (N = 1;Z, P = 0), zero (Z = 1;N, P = 0), or positive (P = 1;N, Z = 0). All other LC-3 instructions leave the condition codes unchanged. Memory-mapped I/O Input and output are handled by load/store (LDI/STI, LDR/STR) instructions using memory addresses to designate each I/O device register. Addresses xFE00 through xFFFF have been allocated to represent the addresses of I/O devices. See Figure A.1. Also, Table A.3 lists each of the relevant device registers that have been identified for the LC-3 thus far, along with their corresponding assigned addresses from the memory address space. Interrupt processing I/O devices have the capability of interrupting the processor. Section A.4 describes the mechanism. Priority level The LC-3 supports eight levels of priority. Priority level 7 (PL7) is the highest; PL0 is the lowest. The priority level of the currently executing process is specified in bits PSR[10:8]. Processor status register (PSR) A 16-bit register, containing status information about the currently executing process. Seven bits of the PSR have been defined thus far. PSR[15] specifies the privilege mode of the executing process. PSR[10:8] specifies the priority level of the currently executing process. PSR[2:0] contains the condition codes. PSR[2] is N, PSR[1] is Z, and PSR[0] is P. Privilege mode The LC-3 specifies two levels of privilege, Supervisor mode (privileged) and User mode (unprivileged). Interrupt service routines execute in Supervisor mode. The privilege mode is specified by PSR[15]. PSR[15] = 0 indicates Supervisor mode; PSR[15] = 1 indicates User mode. Privilege mode exception The RTI instruction executes in Supervisor mode. If the processor attempts to execute an RTI instruction while in User mode, a privilege mode exception occurs. Section A.4 explains what happens. “app-a” — 2003/6/30 — page 523 — #3 A.3 The Instruction Set 523 Supervisor Stack A region of memory in supervisor space accessible via the Supervisor Stack Pointer (SSP). When PSR[15] = 0, the stack pointer (R6) is SSP. User Stack A region of memory in user space accessible via the User Stack Pointer (USP). When PSR[15] = 1, the stack pointer (R6) is USP. A.2 Notation The notation in Table A.1 will be helpful in understanding the descriptions of the LC-3 instructions (Section A.3). A.3 The Instruction Set The LC-3 supports a rich, but lean, instruction set. Each 16-bit instruction consists of an opcode (bits[15:12]) plus 12 additional bits to specify the other information that is needed to carry out the work of that instruction. Figure A.2 summarizes the 15 different opcodes in the LC-3 and the specification of the remaining bits of each instruction. The 16th 4-bit opcode is not specified, but is reserved for future use. In the following pages, the instructions will be described in greater detail. For each instruction, we show the assembly language representation, the format of the 16-bit instruction, the operation of the instruction, an English-language description of its operation, and one or more examples of the instruction. Where relevant, additional notes about the instruction are also provided. “app-a” — 2003/6/30 — page 524 — #4 524 appendix a The LC-3 ISA Table A.1 Notational Conventions Notation Meaning xNumber The number in hexadecimal notation. #Number The number in decimal notation. A[l:r] The field delimited by bit [l] on the left and bit [r] on the right, of the datum A. For example, if PC contains 0011001100111111, then PC[15:9] is 0011001. PC[2:2] is 1. If l and r are the same bit number, the notation is usually abbreviated PC[2]. BaseR Base Register; one of R0..R7, used in conjunction with a six-bit offset to compute Base+offset addresses. DR Destination Register; one of R0..R7, which specifies which register the result of an instruction should be written to. imm5 A 5-bit immediate value; bits [4:0] of an instruction when used as a literal (immediate) value. Taken as a 5-bit, 2’s complement integer, it is sign-extended to 16 bits before it is used. Range: −16..15. LABEL An assembly language construct that identifies a location symbolically (i.e., by means of a name, rather than its 16-bit address). mem[address] Denotes the contents of memory at the given address. offset6 A 6-bit value; bits [5:0] of an instruction; used with the Base+offset addressing mode. Bits [5:0] are taken as a 6-bit signed 2’s complement integer, sign-extended to 16 bits and then added to the Base Register to form an address. Range: −32..31. PC Program Counter; 16-bit register that contains the memory address of the next instruction to be fetched. For example, during execution of the instruction at address A, the PC contains address A+ 1, indicating the next instruction is contained in A+ 1. PCoffset9 A 9-bit value; bits [8:0] of an instruction; used with the PC+offset addressing mode. Bits [8:0] are taken as a 9-bit signed 2’s complement integer, sign-extended to 16 bits and then added to the incremented PC to form an address. Range −256..255. PCoffset11 An 11-bit value; bits [10:0] of an instruction; used with the JSR opcode to compute the target address of a subroutine call. Bits [10:0] are taken as an 11-bit 2’s complement integer, sign-extended to 16 bits and then added to the incremented PC to form the target address. Range −1024..1023. PSR Processor Status Register; 16-bit register that contains status information of the process that is running. PSR[15] = privilege mode. PSR[2:0] contains the condition codes. PSR[2] = N, PSR[1] = Z, PSR[0] = P. setcc() Indicates that condition codes N, Z, and P are set based on the value of the result written to DR. If the value is negative, N = 1, Z = 0, P = 0. If the value is zero, N = 0, Z = 1, P = 0. If the value is positive, N = 0, Z = 0, P = 1. SEXT(A) Sign-extend A. The most significant bit of A is replicated as many times as necessary to extend A to 16 bits. For example, if A = 110000, then SEXT(A) = 1111 1111 1111 0000. SP The current stack pointer. R6 is the current stack pointer. There are two stacks, one for each privilege mode. SP is SSP if PSR[15] = 0; SP is USP if PSR[15] = 1. SR, SR1, SR2 Source Register; one of R0..R7 which specifies the register from which a source operand is obtained. SSP The Supervisor Stack Pointer. trapvect8 An 8-bit value; bits [7:0] of an instruction; used with the TRAP opcode to determine the starting address of a trap service routine. Bits [7:0] are taken as an unsigned integer and zero-extended to 16 bits. This is the address of the memory location containing the starting address of the corresponding service routine. Range 0..255. USP The User Stack Pointer. ZEXT(A) Zero-extend A. Zeros are appended to the leftmost bit of A to extend it to 16 bits. For example, if A = 110000, then ZEXT(A) = 0000 0000 0011 0000. “app-a” — 2003/6/30 — page 525 — #5 A.3 The Instruction Set 525 BaseR 000000 DR DR SR 111111 000000000000 SR BaseR offset6 0000 trapvect8 0 00 BaseR 000000 1 PCoffset11 PCoffset9 PCoffset9 PCoffset9 PCoffset9STI STR TRAP + + + + + + + + + reserved 15 12 11 017 6 5 4 3 210 9 81314 zn p DR SR1 1 imm50101 0000 000 DR SR1 0 00 SR20101 0001 DR SR1 1 imm5 0001 DR SR1 0 00 SR2 DR DR 1100 1010 0110 1110 1001 1100 1000 0011 BaseR offset6 000 111 000000 SR1011 0111 1111 1101 SR 0100 DR0010 0100 PCoffset9 PCoffset9 BR AND ADD ADD AND JMP LD LDI LDR LEA NOT RET RTI ST JSRR JSR Figure A.2 Format of the entire LC-3 instruction set. Note: + indicates instructions that modify condition codes “app-a” — 2003/6/30 — page 526 — #6 526 appendix a The LC-3 ISA ADD Addition Assembler Formats ADD DR, SR1, SR2 ADD DR, SR1, imm5 Encodings 12 11 9 8 6 5 4 3 2 0 15 12 11 9 8 6 5 4 0 15 SR2 0001 DR SR1 1 imm5 0001 DR SR1 0 00 Operation if (bit[5] == 0) DR = SR1 + SR2; else DR = SR1 + SEXT(imm5); setcc(); Description If bit [5] is 0, the second source operand is obtained from SR2. If bit [5] is 1, the second source operand is obtained by sign-extending the imm5 field to 16 bits. In both cases, the second source operand is added to the contents of SR1 and the result stored in DR. The condition codes are set, based on whether the result is negative, zero, or positive. Examples ADD R2, R3, R4 ; R2← R3+ R4 ADD R2, R3, #7 ; R2← R3+ 7 “app-a” — 2003/6/30