I need help with the study guide
(Q1) Write down the name of the main types of hazard in the MIPS pipelining. Explain each of them. Do NOT copy paste from slides or book. Explain it with your own words. (Q2) What are the names and purposes of the five stages of MIPS pipeline? Explain each stage. Do NOT copy paste from slides or book. Explain it with your own words. The name of five stages are fetch, decode, execute, memory access and write back. (Q3) Explain the activities or purposes of the following 3 mux (multiplexers) indicated in the following figure by ellipses and star. Do NOT copy paste from slides or book. Explain it with your own words. (Q4) Assume that; IF ID EX MEM WB 150ps 75ps 100ps 200ps 75ps sw $t0, 0($s1) sub $t0, $t0, $t1 add $t0, $t0, $t1 lw $t0, 0($s1) sub $t0, $t0, $t1 sw $t0, 0($s1) Show all your steps. Do NOT give just numbers. You do NOT get any points if you just give a number! a-) () What is the execution time of the code for non-pipelined processor? Show your calculation results. b-) What is the execution time of the code for pipelined processor? Assume that forwarding is NOT allowed. c-) (What is the execution time of the code for pipelined processor? Assume that forwarding is allowed. (If you forward something, show it by using arrows) (Q5) Assume that your hardware uses branch prediction which always assumes that branch not taken. Show the pipeline of the following code. Forwarding is allowed. Please make the following changes for q5 and solve the problem accordingly. Q5 a-) t2== t0 Q5 b-) t2 != t0 Note 1: Show both cases assuming the values in the registers $t2 == $t3 and $t2 != $t3. Note 2: Use 5 stages for each instruction (including the jump instruction) lw $t0, 0($s0) add $t0,$t0,$t2 beq $t2, $t0, Label lw $t0, 8($s0) sub $t0, $t1, $t2 j Exit Label: sw $t0, 4($s0) Exit: srl $t1, $t0, 2 a-) Assume that the values in the registers $t2 == $t3 b-) Assume that the values in the registers $t2 != $t3 (Q6) Show if the following codes require stalls. Is it possible to avoid stalls by rearranging the instructions? If yes, show the rearranged code and explain it. Assume that forwarding is allowed. Note: Show all the steps. Show initial pipeline stages and final pipeline stages if you rearrange the code. DO NOT just give the rearranged code. Note 2: If the code doesn’t require any stalls, you need to show that as well. a-) add $t0, $t0, $t1 sw $t0, 8($s5) lw $t0, 4($s2) sub $t2, $t1, $t3 b-) add $s0, $t0, $t1 lw $t0, 8($s0) sw $t0, 4($s2) sub $t2, $t1, $t3 add $t5, $t3, $t1 (Q1) Write down the name of the main types of hazard in the MIPS pipelining. Explain each of them. Do NOT copy paste from slides or book. Explain it with your own words. (Q2) What are the names and purposes of the five stages of MIPS pipeline? Explain each stage. Do NOT copy paste from slides or book. Explain it with your own words. The name of five stages are fetch, decode, execute, memory access and write back. (Q3) Explain the activities or purposes of the following 3 mux (multiplexers) indicated in the following figure by ellipses and star. Do NOT copy paste from slides or book. Explain it with your own words. (Q4) Assume that; IF ID EX MEM WB 150ps 75ps 100ps 200ps 75ps sw $t0, 0($s1) sub $t0, $t0, $t1 add $t0, $t0, $t1 lw $t0, 0($s1) sub $t0, $t0, $t1 sw $t0, 0($s1) Show all your steps. Do NOT give just numbers. You do NOT get any points if you just give a number! a-) () What is the execution time of the code for non-pipelined processor? Show your calculation results. b-) What is the execution time of the code for pipelined processor? Assume that forwarding is NOT allowed. c-) (What is the execution time of the code for pipelined processor? Assume that forwarding is allowed. (If you forward something, show it by using arrows) (Q5) Assume that your hardware uses branch prediction which always assumes that branch not taken. Show the pipeline of the following code. Forwarding is allowed. Please make the following changes for q5 and solve the problem accordingly. Q5 a-) t2== t0 Q5 b-) t2 != t0 Note 1: Show both cases assuming the values in the registers $t2 == $t3 and $t2 != $t3. Note 2: Use 5 stages for each instruction (including the jump instruction) lw $t0, 0($s0) add $t0,$t0,$t2 beq $t2, $t0, Label lw $t0, 8($s0) sub $t0, $t1, $t2 j Exit Label: sw $t0, 4($s0) Exit: srl $t1, $t0, 2 a-) Assume that the values in the registers $t2 == $t3 b-) Assume that the values in the registers $t2 != $t3 (Q6) Show if the following codes require stalls. Is it possible to avoid stalls by rearranging the instructions? If yes, show the rearranged code and explain it. Assume that forwarding is allowed. Note: Show all the steps. Show initial pipeline stages and final pipeline stages if you rearrange the code. DO NOT just give the rearranged code. Note 2: If the code doesn’t require any stalls, you need to show that as well. a-) add $t0, $t0, $t1 sw $t0, 8($s5) lw $t0, 4($s2) sub $t2, $t1, $t3 b-) add $s0, $t0, $t1 lw $t0, 8($s0) sw $t0, 4($s2) sub $t2, $t1, $t3 add $t5, $t3, $t1