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Final CSEE W3827 - Fundamentals of Computer Systems Dec 17, 2018 Fall 2018 Prof. Rubenstein This final contains 4 questions (not counting question 0), totaling 120 points. Question 0 gives an additional 5 points. BOOKS, NOTES, ELECTRONIC DEVICES ARE NOT PERMITTED! The time allowed is 3 hours. Please answer all questions in the blue book, using a separate page for each question. Show all work! We are not just looking for the right answer, but also how you reached the right answer. QUESTION 0 (5 points off if you don’t do this): write your name CLEARLY: LAST NAME, FIRST NAME, and UNI on the cover of the blue book and start each of the remaining questions on a new page. If, when sorting the exams according to UNI, yours is sorted incorrectly because of a lack of clarity, you lose the 5 points. Question 1 involves the game rock-paper-scissors. A brief description of the game is as follows: 2 players play and simultaneously select one of three configurations: (R)ock, (P)aper or (S)cissors. If both players select the same configuration (e.g., both select “rock”), then the game is a (D)raw. If they select different configurations, then there will always be one (W)inner and one (L)oser, with rock beating (smashing) scissors, scissors beating (cutting) paper, and paper beating (covering) rock. The game can be played for multiple rounds, providing hours of entertainment. 1 1. (30 pts) You are to build a sequential circuit that implements the strategy of one player (who we call the strategic player) over multiple rounds. In each round (which takes a clock cycle), the circuit does three things: • It chooses a configuration (R,P,S) that the strategic player will play for that round • It reads in a 2-bit input XY that specifies its opponent’s configuration (R,P,S) for that round • It outputs a 2-bit result R1R0 that specifies the strategic player’s outcome (W,L,D) against the opponent. The digital representations of the configuration and outcome are specified as: Opponent Configuration (XY ) Outcome (R1R0) 00 Rock 0X Draw 01 Paper 10 Lose 10 Scissors 11 Win (Note for the outcome, the high-order bit R1 indicates whether someone won the round, and if so, the low order bit then indicates whether the strategic player won). The configuration played in the t+1st round (clock cycle) by the strategic player depends on what both players played in the tth round, and on the outcome (W,L,D). • If the strategic player lost in round t, the configuration in round t+1 matches the configuration in round t. • If the strategic player wins or draws in round t, the configuration in round t + 1 is what would have lost against the opponent in round t. The following table enumerates the 9 scenarios that the 2 players could have played in the round t, and shows the outcome and what the strategic player will play in round t+ 1: Strategic player round t configuration: R R R P P P S S S Opponent round t config: R P S R P S R P S Strategic player outcome [(W)in, (L)ose or (D)raw]: D L W W D L L W D Strategic Player’s round t+ 1 config: S R P S R P S R P (NOTE: The above is not an example of the game being played over a series of rounds, but shows the outcome and next move for all possible configurations of the current round). (a) (20 points) Draw a state machine that implements the sequential circuit described above. (b) (10 pts) Give simplified expressions for the sequential circuit using using JK flip-flops. For full credit, provide simplified expressions for both output bits and inputs to each of the inputs to the JK flip-flops. For your reference, the following table excitation table describes the behavior of a JK flip-flop: J(t) K(t) Q(t+ 1) 0 0 Q(t) 0 1 0 1 0 1 1 1 Q(t) NOTE: Part (a) is 2/3 of the points for this problem, and is a lot less grunt work. Be sure to look at other problems before sinking too much time into part (b). 2 S R E S R k 2k S R E S R E S R E S R E S R E S R E S R E S R E… 32 k-to-2k Decoder k k 32 32 W Data-In Data-Out Write-Addr Read-Addr 2. (30 pts) The traditional memory cell (an SR latch with enable) is depicted above on the left, and the manner in which these cells are enabled in a memory chip with 2k 32-bit words is shown on the figure in the middle (the read and write logic is not shown). Suppose we wish to design a memory chip, as depicted in the right figure, that takes 2 addresses AW and AR such that the chip can simultaneously write data to address AW while it reads from address AR. (a) (15 pts) Show how to modify the traditional memory cell to implement this functionality (i.e., how would you redraw the left figure?) (b) (15 pts) Show how to modify the memory chip’s enable circuitry such that you can separately select an address for writing and another for reading (i.e., how would you redraw the middle figure?) You do not need to show the Read or Write Logic. You only need to show the “enable” portion of the memory. 3 Datapath Control Scheme 38 8 3. (30 pts) Consider the single-cycle architecture as pictured above. (a) (10 pts) Suppose we wish to add a new instruction, bme which stands for branch-if-memory-equal, branch- ing only when the specified register’s stored value equals the value stored in the specified memory location, and has the form: bme $r1, C($r2), LABEL It performs the exact same functionality as the following snippet using existing MIPS instructions: lw $t0, C($r2) beq $t0, $r1, LABEL There are at least three main challenges to implementing this instruction into the existing single-cycle architecture. Describe two of them. NOTE: for full credit, the two you describe must be correct. If you list three and n of them are right, you get at most n/3 of the credit. (b) (20 pts) Suppose we wish to add a different new instruction, sbz, which stands for subtract and branch-if- zero, and has the form: sbz $r1, $r2, LABEL and performs the functionality as the following existing snippet: sub $r2, $r1, $r2 beq $r2, $zero, LABEL Starting with the an existing MIPS instruction (other than sbz), explain how to alter that instruction to arrive at sbz. Specifically, what signals would you change coming out of Control? And what hardware would you need to add, if any? 4 Simplified Pipeline w. Forwarding Paths �51 00 00 01 01 10 10 00: regular operation - take from ID/EX stage 01: data forwarding from MEM/WB stage 10: data forwarding from EX/MEM stage 4. (30 pts) The above figure shows a portion of the pipeline architecture with data-forwarding implemented. The green arrow points to a region where a MUX that allows one to select between the second register value and a constant exists (it was the same location as it would be in the single-cycle architecture). Consider the following snippet of code: add $s0, $zero, $zero addi $s1, $zero, 40000 lw $s0, 0($s1) sw $s0, 1000($s1) and suppose that the value stored in memory at address 40000 equals 100. Suppose the designer figures that because data forwarding is implemented, he/she doesn’t need to stall any of the above instructions when running them through the pipeline. (a) (10 pts) What registers and/or memory locations will have incorrect values stored as a result of not imple- menting the stall, and what (incorrect) value could occur? Explain in 1 sentence how that particular value occurred instead of the correct value. (b) (10 pts) It is possible to add additional forwarding logic such that a stall would not be necessary. Indicate where and how. Either draw a picture of the circuitry where a change is being made, or simply provide a short, clear description of the change. (c) (10 pts) Does the above change in part (b) prevent all stalls due to data dependencies? If so, give a short, 1 sentence explanation as to why. If not, give an example MIPS code snippet that would still require a stall due to a data dependence. 5 You have reached the end of the exam. Have a great Winter Break! 6 End-of-term Exam CSEE W3827 - Fundamentals of Computer Systems April 30, 2019 and May 2, 2019 Spring 2019 Prof. Rubenstein This portion of the final contains 3 questions (not counting question 0), totaling 90 points. Question 0 gives an additional 10 points. BOOKS, NOTES, ELECTRONIC DEVICES ARE NOT PERMITTED! The time allowed is 150 minutes. Please answer all questions in the blue book, using a separate page for each question. Show all work! We are not just looking for the right answer, but also how you reached the right answer. SECTION 1 students: Please put your UNI on your exam copy and submit it at the end. Do not take with you! YOUR UNI: SECTION 2 students: You may keep your copy of the exam. Some advice: • Be sure to leave some time to work on each problem. The right answer to each problem does not require a very long answer. • Be sure to start every problem. And take some time to think about how to set the problem up before you start writing. 0. (5 pts) Do the following in the blue book: (a) CLEARLY write your • name and UNI • lecture section number (1 for 10:10 class, 2 for 11:40 class) on the front cover. • P-credit TA and section number (or day/time) (b) start each numbered question’s solution on a new page. So question 2 should start on a new page, question 3 on a new page, etc. (c) label solutions (e.g., 2a, 2b, 2c or 2a, b, c) 1 32 A = A31A30…A2A1A0 Addr W 16 16 16 16 F Data-In High Data-Out High Data-In Low Data-Out Low Din Dout 1. (30 pts) The memories designed in class could read and write one full word of data (32 bits) at a time. To extend the design to also handle half-words (16 bits), an additional 1-bit input F is added to the chip as shown above. • When F = 1 the chip operates in traditional full-word mode, with A = A31A30 · · ·A3A2A1A0 mapping to the 4 byte addresses associated with word address A31A30 · · ·A3A200. When W = 1, 32-bit Din is written to the word of memory at this address. 32-bit Dout outputs the value stored at this address. • When F = 0, the chip operates in half-word mode. Here, address bit A1 now plays an important role