I need a verilog coding assignment done
Microsoft Word - Lab 5 Revised 4/8/2020 by Jerry A. Yang Lab 5: Adders EE 316: Digital Logic Design Overview This lab is intended for you to design various datapath components in Verilog. By the end of this lab, you should be able to: describe and implement a multiply-accumulate circuit. design datapath components in Verilog and use them in other datapath components. design a load register that stores variable input in Verilog. This lab will require previous knowledge of adders and load registers. Be sure to review them before starting the lab. NB: Traffic on the Linux server may slow your connection and Vivado speed down. Please make sure to account for this in managing your time to complete the lab. Background Ripple-carry and carry-lookahead adders are two fundamental types of adders. In this section, we will discuss how they are implemented. Ripple-Carry Adders Ripple-carry adders (RCAs) are essentially a bunch of one-bit full adders in series. A one-bit full adder has three inputs: ?, ?, and ? . ? and ? are the two operands, and ? is the carry-in value. The outputs of the adder are the sum ? = ? ⊕ ? ⊕ ? and the carry-out ? = ?? + ?? + ??. If you cascade many full adders together as shown in Figure 1, you can get an ?-bit adder that has ? + 1 outputs (the ?-bit sum and the final carry-out). While ripple-carry adders are easier to design and use less gates, the time it takes to compute a sum using a ripple-carry adder is strictly a function of long it takes for the final carry-out to be calculated. If you want to calculate a 16-bit sum, you would have to wait until all 16 full adders in the 16-bit ripple-carry adder update before getting the correct carry-out, which may take an extremely long time. The critical path of a circuit is the path in the circuit that takes the longest time to calculate. For the ?-bit RCA, the critical path is the carry-out, as it depends on both inputs ? and ? and the carry-in - which depends on the previous full adder's carry-out, which depends on the previous 2 full adder's carry-in, and so on and so forth. The final carry-out thus depends on the initial carry- in, which must ripple (a.k.a. propagate) through the full adders as each one computes. Calculating the carry-out is the primary reason RCAs are not desired: it takes a long time to do. Carry-Lookahead Adders To solve the delay issues of RCAs, carry-lookahead adders (CLAs) “pre-calculate” all the carry- ins in advance based on the bits in the two operands. Two new values are used to calculate the sum and carry-out in the CLA: the “propagate” bit ? and the “generate” bit ? : ? = ? ⊕ ? ? = ? ? . These values are calculated BEFORE the computation of the sum bits is completed. Once the propagate and generate bits are calculated, the sum and carry-out bits can be computed: ? = ? ⊕ ? ? = ? + ? ? . Furthermore, we can expand ? , ? , and ? in terms of ? , ? , and ? by recursively substituting the equations for ? . For example, for ? and ? , ? = ? + ? ? = ? + ? (? + ? ? ) = ? + ? ? + ? ? ? ? = ? ⊕ (? + ? ? + ? ? ? ) NB: In this lab, we expect you to expand all sum and carry bits to the sum-of-products forms shown above. If you leave the equations in nested form (i.e. ? + ? (? + ? ? )), you will get incorrect answers for checkout questions. The block diagram in Figure 2 shows the dataflow of a CLA. Figure 2. Carry-Lookahead Adder As a result of the substitution property, even though the equations may become extremely long, it is theoretically possible to write an ?-bit CLA using no more than four stages of gates, thus reducing the critical path of the adder. However, the trade-off is that the equations become long, which in hardware, represents more gates. 3 As computer systems become increasingly complex and require increasingly fast processing speeds, the trade-off between area and critical path delay becomes increasingly favorable to area. Why? Because current microprocessors have billions upon billions of transistors that can be used implement any desirable circuit - there is no lack of area for circuits to be placed, but there is an upper bound on how fast a circuit can calculate a value. A faster computer will want to shorten critical path delays as much as possible, and without the concern for area, a carry-lookahead adder is almost always the better option between the two adder types. Procedure Part A: Ripple-Carry Adder (RCA) In this section, you will build a 4-bit ripple-carry adder using dataflow modeling. Your two operands will come on SW[7:4] and SW[3:0], and your carry-in bit will come on SW[8]. Display the sum and carry-out as a 5-bit pattern on the LEDs. Your sum should update only when the center button btnC is pressed. For example, if your switch input is SW[7:4]=4’b0111 and SW[3:0]=4’b0101, then when btnC is pressed, your output should be LED[4:0]=5’b01100 (LEDs 2 and 3 should be on). If SW[3:0] changes to 4’b0100, the LEDs should still contain LED[4:0]=5’b01100 until btnC is pressed, at which point, they will change to LED[4:0]=5’b01011. For this part, you are only allowed to use bitwise operators in Verilog: & (AND), ∼ (NOT), | (OR), ˆ (XOR). 1. Design a module named loadreg.v that captures the functionality of a load register. Your module should look something like the code below. Be sure to adjust the input and output bit vectors to the appropriate values. Note that this is a behavioral implementation of a load register; a structural/dataflow model would include declaring the gates for the SR latch, D latch, and D flipflop. module loadreg( input clk, load, input D, output reg Q); initial Q = 0; always @(posedge clk) begin if(load) Q <= d; end endmodule 2. design a module that implements a one-bit full adder with carry-in and carry-out using dataflow modeling. your module declaration should look like: module adder( input a, b, cin, output s, cout); do not edit the module declaration in your code. 3. design a top module named rca.v that implements a 5-bit rca using your module from the previous step. your module declaration should look like this: module rca ( input clk, load, input [3:0] a, b, input cin, 4 output [4:0] total); do not edit the module declaration in your code. 4. fill out the table below that showcases various input combinations. use the combinations below in your testbench to verify your adders’ functionality. name your testbench tb_adders.v a b cin sum cout 0000 0000 0 0000 0001 1 0001 0101 0 0111 0111 0 1000 0111 1 1100 0100 0 1000 1000 1 1001 1010 1 1111 1111 0 to assist in waveform readability, change the radix/base system that the waveform displays values in. to do so, select the signal in the waveform window, right-click to see the dropdown menu, hover over the word “radix”, and click “unsigned decimal”. the waveform should now display the signal values in unsigned decimal. do this for all bit vectors in your waveform. below is a snippet of the waveform that we expect (minus the load register functionality; you will need to show that in your waveforms as well): 5. once you get your waveforms and testbench working, add a constraints file (adder_constrs.xdc) and generate the bitstream to make sure that the bitstream will be successful. note that you will reuse the testbench and constraints file for part b. 6. once you are almost certain that your code is working, use the verification script provided on the ece linux servers to test your adder. part b: carry-lookahead adder (cla) in this part, you will build a 4-bit carry-lookahead adder using dataflow modeling. use the same input and output parameters as the rca. remember to pass the output of the cla into the load register. 1. derive the sum and carry-out bits ? through ? and ? through ? for the 4-bit cla in terms of propagate bits ? , generate bits ? , and the carry-in bit ? . make sure that your expressions are in sum-of-products form and not in nested form; you need to 5 expand all the equations out, as done for ? and ? in the background section on the cla. (it's not as tedious as you think; there is a pattern.) 2. design a top module named cla.v that implements a 5-bit cla using dataflow modeling. your module declaration and first line of code should look like this: module cla ( input clk, load, input [3:0] a, b, input cin, output [4:0] total); wire [3:0] g, p, c; you may modify the wire declarations to fit your module needs, but you may not modify the module declaration. 3. add to the testbench in part a to simulate and test your cla; do not create a separate simulation source. test both the rca and the cla at the same time: instantiate both in the testbench and declare additional wires to capture the extra outputs. your final simulation screenshot should show d;="" end="" endmodule="" 2.="" design="" a="" module="" that="" implements="" a="" one-bit="" full="" adder="" with="" carry-in="" and="" carry-out="" using="" dataflow="" modeling.="" your="" module="" declaration="" should="" look="" like:="" module="" adder(="" input="" a,="" b,="" cin,="" output="" s,="" cout);="" do="" not="" edit="" the="" module="" declaration="" in="" your="" code.="" 3.="" design="" a="" top="" module="" named="" rca.v="" that="" implements="" a="" 5-bit="" rca="" using="" your="" module="" from="" the="" previous="" step.="" your="" module="" declaration="" should="" look="" like="" this:="" module="" rca="" (="" input="" clk,="" load,="" input="" [3:0]="" a,="" b,="" input="" cin,="" 4="" output="" [4:0]="" total);="" do="" not="" edit="" the="" module="" declaration="" in="" your="" code.="" 4.="" fill="" out="" the="" table="" below="" that="" showcases="" various="" input="" combinations.="" use="" the="" combinations="" below="" in="" your="" testbench="" to="" verify="" your="" adders’="" functionality.="" name="" your="" testbench="" tb_adders.v="" a="" b="" cin="" sum="" cout="" 0000="" 0000="" 0="" 0000="" 0001="" 1="" 0001="" 0101="" 0="" 0111="" 0111="" 0="" 1000="" 0111="" 1="" 1100="" 0100="" 0="" 1000="" 1000="" 1="" 1001="" 1010="" 1="" 1111="" 1111="" 0="" to="" assist="" in="" waveform="" readability,="" change="" the="" radix/base="" system="" that="" the="" waveform="" displays="" values="" in.="" to="" do="" so,="" select="" the="" signal="" in="" the="" waveform="" window,="" right-click="" to="" see="" the="" dropdown="" menu,="" hover="" over="" the="" word="" “radix”,="" and="" click="" “unsigned="" decimal”.="" the="" waveform="" should="" now="" display="" the="" signal="" values="" in="" unsigned="" decimal.="" do="" this="" for="" all="" bit="" vectors="" in="" your="" waveform.="" below="" is="" a="" snippet="" of="" the="" waveform="" that="" we="" expect="" (minus="" the="" load="" register="" functionality;="" you="" will="" need="" to="" show="" that="" in="" your="" waveforms="" as="" well):="" 5.="" once="" you="" get="" your="" waveforms="" and="" testbench="" working,="" add="" a="" constraints="" file="" (adder_constrs.xdc)="" and="" generate="" the="" bitstream="" to="" make="" sure="" that="" the="" bitstream="" will="" be="" successful.="" note="" that="" you="" will="" reuse="" the="" testbench="" and="" constraints="" file="" for="" part="" b.="" 6.="" once="" you="" are="" almost="" certain="" that="" your="" code="" is="" working,="" use="" the="" verification="" script="" provided="" on="" the="" ece="" linux="" servers="" to="" test="" your="" adder.="" part="" b:="" carry-lookahead="" adder="" (cla)="" in="" this="" part,="" you="" will="" build="" a="" 4-bit="" carry-lookahead="" adder="" using="" dataflow="" modeling.="" use="" the="" same="" input="" and="" output="" parameters="" as="" the="" rca.="" remember="" to="" pass="" the="" output="" of="" the="" cla="" into="" the="" load="" register.="" 1.="" derive="" the="" sum="" and="" carry-out="" bits="" through="" and="" through="" for="" the="" 4-bit="" cla="" in="" terms="" of="" propagate="" bits="" ,="" generate="" bits="" ,="" and="" the="" carry-in="" bit="" .="" make="" sure="" that="" your="" expressions="" are="" in="" sum-of-products="" form="" and="" not="" in="" nested="" form;="" you="" need="" to="" 5="" expand="" all="" the="" equations="" out,="" as="" done="" for="" and="" in="" the="" background="" section="" on="" the="" cla.="" (it's="" not="" as="" tedious="" as="" you="" think;="" there="" is="" a="" pattern.)="" 2.="" design="" a="" top="" module="" named="" cla.v="" that="" implements="" a="" 5-bit="" cla="" using="" dataflow="" modeling.="" your="" module="" declaration="" and="" first="" line="" of="" code="" should="" look="" like="" this:="" module="" cla="" (="" input="" clk,="" load,="" input="" [3:0]="" a,="" b,="" input="" cin,="" output="" [4:0]="" total);="" wire="" [3:0]="" g,="" p,="" c;="" you="" may="" modify="" the="" wire="" declarations="" to="" fit="" your="" module="" needs,="" but="" you="" may="" not="" modify="" the="" module="" declaration.="" 3.="" add="" to="" the="" testbench="" in="" part="" a="" to="" simulate="" and="" test="" your="" cla;="" do="" not="" create="" a="" separate="" simulation="" source.="" test="" both="" the="" rca="" and="" the="" cla="" at="" the="" same="" time:="" instantiate="" both="" in="" the="" testbench="" and="" declare="" additional="" wires="" to="" capture="" the="" extra="" outputs.="" your="" final="" simulation="" screenshot="" should="">