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Copyright 2021, All rights Reserved, not for distribution. For use with UCD ECS-154a Fall 2021 Only. OVERVIEW You have been provided with a Logisim file that provides the front panel shown above along with the implemented front panel controller. This controller will allow you to step through instructions, run the CPU, and reset the CPU. You are also provided with the ROM that is the instruction memory on the front panel. The reason for putting the ROM outside of the CPU is to make loading programs less tedious. You have been provided with an empty shell for the CPU module. Building this module is your task for this lab. Our focus in this lab is in building a CPU and understanding the detail involved. Consequently, you are not restricted to using simple logic gates. You may use many of the powerful features available in Logisim Evolution 2.15. Do not worry about minimization of gates, rather, focus on building a reliable CPU and understanding the relationship between programming and CPU architecture. SUBMISSION Full submission details will be provided on Canvas. However, you can expect three things with this project. First, you must do a writeup, second, you must submit a .circ file created and edited only with Logisim Evolution version 2.15, and third, you will be creating a short (two minutes max runtime) of you demonstrating the operation of your CPU. BUILD THE INSTRUCTION FETCH UNIT Your first task is to build out the instruction fetch unit. The instruction fetch unit is responsible for fetching the next instruction to execute. Figure 7.8 in your book gives you a rough outline of the functionality of this module. The JMP input shown here is, in essence, the PCSrc controller output shown in figure 7.8. This line goes high whenever the CPU is executing some kind of branch. The jump address to be loaded into the program counter is provided via the WBBus input. Since this unit will contain the program counter register, it is essential that it be connected to the system-wide Reset and Clk signals. This way, when you reset the CPU, the program counter will reset to zero. A discussion of how this works starts on page 393 of your textbook. While building this it’s important to keep some details in mind. A real ARM CPU uses byte aligned memory and 32-bit data words. This means that the next instruction is at PC+4. We are using word-aligned memory with 16-bit words. So, for us, the next instruction is at the next location in memory. Also, in ARM, R15, which is the PC register, always holds PC+8, or two instructions ahead. Your book mentions that this is for historical reasons. Consequently, our last register, R7, will always point to the next instruction to be executed, PC+1. This is why we have a PCPlus1 output. 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