How many hardware interrupt requests can a single interrupt controller IC 8259A process? (a) 8 (b) 15 (c) 16 (d) 64 In DMA operation, data transfer takes place between (a) memory and CPU (b) CPU and...

How many hardware interrupt requests can a single interrupt controller IC 8259A process?

(a) 8 (b) 15 (c) 16 (d) 64

In DMA operation, data transfer takes place between

(a) memory and CPU (b) CPU and I/O

(c) I/O and Memory (d) different CPUs

(v) The programmable interval timer is

(a) 8253 (b) 8251 (c) 8250 (d) 8275