HONOR CODE I have not used any online resources during the exam. I have not obtained any help either from anyone in the class or outside when completing this exam. No sharing of notes/slides/textbook...

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HONOR CODE I have not used any online resources during the exam. I have not obtained any help either from anyone in the class or outside when completing this exam. No sharing of notes/slides/textbook between students. NO SMARTPHONES. CANVAS ANSWERS WILL BE LOCKED AFTER 1ST TRY. Questions Sheet. Read all of the following information before starting the exam: For each question fill out the appropriate choice. If no text box is provided, you do not need to fill out written text. Show all work, clearly and in order, if you want to get full credit. I reserve the right to take off points if I cannot see how you logically got to the answer (even if your final answer is correct). Circle or otherwise indicate your final answers. Please keep your written answers brief; be clear and to the point. I will take points off for rambling and for incorrect or irrelevant statements. This test has six problems. HONOR CODE Questions Sheet. Section Virtual Memory 22 points. Canvas Q1-Q22 Common questions. Canvas Q1-Q2 For the virtual address 0x2cade0 answer the following Canvas Q3-Q12 For the virtual address 0x301754 answer the following. Canvas Q13-Q22 B. Section Cache I Questions. 15 points. Canvas Q23-Q25 23. What is the miss rate for loop 1? (Assume that only loop 1 runs). 5 points 24. What is in the cache at the end of loop 1? 5 points 25. What is the miss rate for loop 2 ? Assume that loop 1 has already run to completion and has warmed up the cache. 5 points C. Section Cache II Questions. 20 points. Canvas Q26-Q31 26. Assuming the total size of the physical address is 32 bits. What is the number of bits required by tag, index and offset (4 points) 27. What is the hit rate of this direct-mapped cache? (4 points) 28. What type of misses occur (Conflict, Compulsory, Capacity) ? (2 points) 29. What is the hit rate a 2-way set associative cache. 512 bytes. 8 words/block. (4 points) 30. What type of misses occur (Conflict, Compulsory, Capacity) in the 2-way cache ? (2 points) 31. Now consider a 4-way set associative cache. 512 bytes. 8 words/block.What is the hit rate ? (4 points) D. RISC-V Pipeline 20 points. Canvas Q32-Q41 32. In which cycle does  addi x18,x0,0  (instruction 2) run the EX stage ? 33. In which cycle does  beq x9,x18,exit  (instruction 3) read the registers? 34. In which cycle does the  lw x9, 10(x8)  (instruction 4) start the IF stage ? 35. In which cycle does the  lw x9, 10(x8)  read the registers ? 36. In which cycle does the  xor x9, x9, x18  (instruction 5) reach the IF stage ? 37. In which cycle does the  xor x9,x9,x18  (instruction 5) read the registers ? 38. In which stage is  sw x9, 10(x8)  stalled and how many cycles? 39. In which cycle does the  sw x9, 10(x8)  (instruction 6) write the memory location ? 40. How many instructions are stalled due to data hazards ? 41. How many cycles do we have stall in total for this program ? i.e., Consider a program with 6 instruction and no hazards and ran to completion in T cycles. This program completed in T_hazard cycles. What is (T_hazard - T)? E. RISC-V Datapath 20 points. Canvas Q42-Q51 42. What is encoding that supports  RELU  ? 43. Which instruction field can be written to memory in the baseline pipeline? 44. Consider the following modifications to the source  Reg[]  inputs. Which configuration will allow this instruction to execute correctly without breaking the ex-ecution of other instructions in our instruction set? 45. Consider the following modifications to the  Branch . Which con-figuration will allow this instruction to execute correctly without breaking the ex-ecution of other instructions in our instruction set? Branch calculates  A==B  and  A