COIT 20246 ASSIGNMENT SUBMISSION Due date: Part: Written Assessment Weighting: 30% of total assessment. Submission: Electronic (see course website for details) Instructions It will be necessary to use...

Week 1
    
    Title and Reference:
A killer flaw
side-channel, R. (2018). Reading privileged memory with a side-channel. [online] Googleprojectzero.blogspot.in. Available at: https://googleprojectzero.blogspot.in/2018/01/reading-privileged-memory-with-side.html [Accessed 18 Apr. 2018].
    Summary:
The timing for the CPU data cache can be misused and it can be efficiently mistreated to leak information out of the problem which leads to the random virtual memory reading and causes to the vulnerability passing through all the security boundaries at various points and contexts. Until now the 3 known errors of the variants are understood:
- Variant 1: bounds check bypass (CVE-2017-5753)
- Variant 2: branch target injection (CVE-2017-5715)
- Variant 3: rogue data cache load (CVE-2017-5754)
The basic principles behind the variant 1 is determined by a POC in the userspace on the INTEL Haswell Xeon CPU, the AMD PRO CPU, an ARM Cortex A57 and the the AMD FX CPU too. The ability to read the data inside miscalculated working within the same area of execution without the crossing of the boundaries which are specified are done by the POC.
The POC assigned to the Variant 1 the one which is running with normal user privileges and working with the kernel which belongs to Linux with a config which is distro-standard is capable of performing reads in a 4GiB range. In the virtual memory of the Intel Haswell Xeon CPU. If the BPF JIT in the kernel is active, in the config mode which is not default, it would also be working on the works on the AMD PRO CPU. around 2000 bytes per second is the speed at which the kernel virtual memory would read On the Intel Haswell Xeon CPU around after 4 seconds of the startup time
    Week 2
    
    Title and Reference:
LISA, a modern computer in olden times
Lisa, A. (2018). Apple Lisa - Mac History. [online] Mac History. Available at: http://www.mac-history.net/apple-history-2/apple-lisa/2007-10-12/apple-lisa [Accessed 18 Apr. 2018].
    Summary:
In the year 1980, Apple Lisa was one of the few computers that were being designed. The acronym :LISA” stood for “Local Integrated Software Architecture” , plus it was the name of Steve Job’s [ co –founder of apple ]daughter.
It was the year 1978 when project LISA was initiated and it evolved into being a project design which was a powerful computer in itself. It had a graphical user interface that would be targeted towards business customers. It was in the year 1980 that Steve jobs was pushed out of the LISA project and hence Steve jobs joined the MAC project. The Lisa was a more advanced and heavily expensive than the MAC project. It included the cooperative multitasking, protected memory, and a more sophisticated hard disk. The LISA had a built in screensaver and also included an advanced 2mb of Ram, a higher resolution display and also expansion slots. There were many years to go before these features were to be implemented in the MAC. An example would be that the protective memory did not appear in MAC until MAC X OS which was released in the year 2001. The complexity of LISA OS and the weight of the programmes used up Motorola’s 5Mhz 68000 microprocessor, so the system felt sluggish, mainly while scrolling the documents
    Week 3
    
    Title and Reference:
LPWAN’s Modern use in IOT
i-SCOOP. (2018). Internet of Things network technologies: LPWAN wireless IoT guide. [online] Available at: https://www.i-scoop.eu/internet-of-things-guide/lpwan/ [Accessed 18 Apr. 2018].
    Summary:
There are multiple cases in the history of technology which uses LPWAN. In the current technological advancement stage, LPWAN is used in the IOT devices. There are multiple cases, specially in industrial use of IOT where LPWAN’s are used. The applications need cheap mobile low power with long range of connectivity. Due to cellular technology being very much exoensive, it was not suitable for the IOT devices. The IOT developers started building their own netweork with the low bandwidth. A whole new ecosystem consisting of partners and supporters is present which also includes the major telecomm firms and the industry experts and giants. The LoRA alliance was formed by Semtech. It was Semtech which patented the CSS technology which was the source for generation of LoRA wide area network. Similarly, Sigfox was developed which is based on a different model structure. It is using a different technology for its sigfox network but the parent company which is also Sigfox utilises an entirely different business model. Weightless(SIG) is one of the major players in the IOT ecosystem which uses LPWAN. Weightless represents a group of companies and not a single entity. It is an organisation which does not work for profit and has dedicated its work in finding the ‘best’ IOT connectivity device technology. Ingenu is the last player in the IOT space. Ingenu was previously known as RPMA which is a short form of Random Phase Multiple Access. Machine to Machine is the strong point of Ingenu and works on the biggest IOT Networks
    Week 4
    
    Title and Reference:
The Session Initiation Protocol
Cisco. (2018). The Session Initiation Protocol - The Internet Protocol Journal - Volume 6, Number 1. [online]...