Given the single-cycle datapath below, answer the following questions. Assume that I-Mem, Add, Mux, ALU, Regs, D-Mem, and Control blocks have latencies of 300ps, 100ps, 20ps, 120ps, 150ps, 250ps, and...

1. Given the single-cycle datapath below, answer the following questions.

1. Assume that I-Mem, Add, Mux, ALU, Regs, D-Mem, and Control blocks have latencies of 300ps, 100ps, 20ps, 120ps, 150ps, 250ps, and 100ps, respectively. What is the execution time for the instruction
   SUB X3, X1, X2?

1. Given instruction
   SUB X3, X1, X2,
   what is the register number supplied the register file’s “Read Register 1” input? Is this register actually read? How about “Read register 2”?

1. Given instruction
   STUR X1, [X2, #4],
   what is the register number supplied the register file’s “Write Register” input? Is this register actually written?

1. Given instruction word 0xf8014061, what is the output of the “Shift left 2” unit?

1. Given two instructions
   SUB X3, X1, X2
   and
   LDUR X1, [X2, #4], what are the values of control signals
   Reg2Loc, MemtoReg, ALUSrc, RegWrite, and Branch
   for each instruction?

CPSC431 Exam#3 Name_____________ 1. (20 points) Given the single-cycle datapath below, answer the following questions. 1) Assume that I-Mem, Add, Mux, ALU, Regs, D-Mem, and Control blocks have latencies of 300ps, 100ps, 20ps, 120ps, 150ps, 250ps, and 100ps, respectively. What is the execution time for the instruction SUB X3, X1, X2? 2) Given instruction SUB X3, X1, X2, what is the register number supplied the register file’s “Read Register 1” input? Is this register actually read? How about “Read register 2”? 3) Given instruction STUR X1, [X2, #4], what is the register number supplied the register file’s “Write Register” input? Is this register actually written? 4) Given instruction word 0xf8014061, what is the output of the “Shift left 2” unit? 5) Given two instructions SUB X3, X1, X2 and LDUR X1, [X2, #4], what are the values of control signals Reg2Loc, MemtoReg, ALUSrc, RegWrite, and Branch for each instruction? 2. (24 points) Answer the following questions. 1) Assume negligible delays for muxes, control unit, sign extend, PC access, shift left 2, wires, setup and hold times except: Instruction Memory (300ps), Data Memory (250 ps), ALU (200 ps), Register File access (reads or writes) (100 ps). Find out the total execution time for different types of instructions by filling out the following table. Instr I-Mem Reg Rd ALU op D-Mem Reg Wr Total LDUR STUR R-type CBZ 2) Based on what you have done in problem 1), which instruction determines the critical path. What is the clock cycle time for a single-cycle datapath implementation? 3) If we convert the single-cycle datapath to pipelined datapath using the 5-stage IF, ID, EX, MEM, WB LEGv8 design, what is the clock cycle time for the pipelined datapath? 4) What is the total execution time of SUB X3, X1, X2 for non-pipelined datapath and pipelined datapath (assuming no data dependency), respectively? 5) If we can improve the latency of one of the stages by 20%, which stage should it be? What is the clock cycle time for the pipelined datapath after the improvement? 6) Assume that instructions executed by a pipelined processor are broken down as below ADD CBZ LDUR STUR 35% 15% 30% 20% Assuming there are no stalls, how often (percentage of all cycles) do we use the data memory? 3. (20 points) Given the following sequence of instructions, answer questions. I1:LDUR X2, [X1, #40] I2:ADD X6, X4, X2 I3:SUB X8, X5, X2 1) Identify all the RAW (read after write) data dependences. 2) Assume there is no forwarding in this pipelined processor, indicate hazards and add nop instructions to eliminate them. 3) Assume there is full forwarding in this pipelined processor, indicate hazards and add nop instructions to eliminate them. How many cycles will the sequence of instructions take to execute on the standard five-stage ARM pipeline? 4) Assume, due to circuit constraints, that the forwarding wire from the memory stage back to the execute stage is omitted from the pipeline. How many cycles will the program take to execute on the standard ARM pipeline? 5) Draw the pipeline execution diagram for this code, assuming there is full forwarding in this pipelined processor. 4. (20 points) This problem covers your knowledge of branch prediction. 1) The figure below illustrates 1-bit predictor: Last-taken predicts taken when 1. Fill out the table below for the predicator. The execution pattern for the branch is NNNTTTNN Execution Time Branch Execution State Before Prediction Correct or Incorrect State After 0 N 0 1 N 2 N 3 T 4 T 5 T 6 N 7 N 2) What is the prediction accuracy of the predictor? 3) If we have another predictor that predict always not taken, what is the prediction accuracy of this predictor given the same execution pattern (i.e. NNNTTTNN)? 4) Assume that 1) the frequency of branch instructions in a program is 10%; 2) the branch outcomes are determined at the MEM stage; and 3) the prediction accuracy of a given predictor is 70%. What is the extra CPI due to mispredicted branches with the predictor? 5. (16 points) Given the 5-stage pipelined ARM datapath, answer the following questions. ( 1. Cut here ) ( 2. Cut here ) 1) For the ARM datapath shown above, two lines are marked with “X”. For each one: a. Describe in words the negative consequence of cutting this line relative to the working, unmodified processor. b. Provide a snippet of code that will fail 2) Indicate the stage at which the branch outcomes are determined in the above datapath. How many cycles will be spent stalling for each mispredicted branch? Using the above figure to explain how to stall the pipeline for one cycle when a hazard is detected.