Given the following latencies-- I-Mem: 200ps, Add: 70ps, Mux: 20ps, ALU: 90ps, Regs: 90ps, D-Mem: 250ps, Sign-Extend: 15ps, Shift-Left-2: 10ps. If the only thing we need to do in a processor is fetch...

Given the following latencies-- I-Mem: 200ps, Add: 70ps, Mux: 20ps, ALU: 90ps, Regs: 90ps, D-Mem: 250ps, Sign-Extend: 15ps, Shift-Left-2: 10ps.

If the only thing we need to do in a processor is fetch consecutive instructions, what would the cycle time be?