Give reasonable device widths of the comparator in Fig. 10.20 so that the first stage has a gain of 5 and so that the latch-and-track stage has a gain of 10 when in track mode and a loop gain of 4...

Give reasonable device widths of the comparator in Fig. 10.20 so that the first stage has a gain of 5 and so that the latch-and-track stage has a gain of 10 when in track mode and a loop gain of 4 when in latch mode. Assume the input transistors are 25-μm wide and that the bias current of the first stage is .