(For those with knowledge of computer architecture.) Write a parallel program to model a fivestage RISC processor (reduced instruction set computer), as described in Hennessy and Patterson...

(For those with knowledge of computer architecture.) Write a parallel program to model a fivestage RISC processor (reduced instruction set computer), as described in Hennessy and Patterson (2003). The program is to accept a list of machine instructions and shows the flow of instructions through the pipeline, including any pipeline stalls due to dependencies/resource conflicts. Use a single valid bit associated with each register to control access to registers, as described in Wilkinson (1996).