For a processor with a 32-bit address bus and a 64-bit data bus, 32 bytes of "line size" and a total capacity of 2MByte "cache" memory are used. For each of the "cache map" techniques given below,...

For a processor with a 32-bit address bus and a 64-bit data bus, 32 bytes of "line size" and a total capacity of 2MByte "cache" memory are used. For each of the "cache map" techniques given below, find how the physical address will be partitioned and how many bits will be used for each partition.

a) fully associative

b) direct mapped