Figure P5.23 shows how we can exploit the foldedcascode technique to realize a two-stage op amp in which all signal-processing transistors are nMOSFETs, which are faster than pMOSFETs because n is two...

Figure P5.23 shows how we can exploit the foldedcascode technique to realize a two-stage op amp in which all signal-processing transistors are nMOSFETs, which are faster than pMOSFETs because n is two to three times higher than p. Signal coupling from the differential pair M1-M2 to the current-mirror load M3-M4 takes place via the level-shifting voltage sources denoted as VLS (omitted for simplicity, the biasing circuitry is modeled via the dc sources V1 and V2). (a) Assuming k9 n 5 150 A/V2 , k9 p 5 60 A/V2 , Vtn 5 2Vtp 5 0.6 V, 9 n 5 0.02 m/V, 9 p 5 0.04 m/V, and L 5 0.75 m throughout, specify suitable values for W1 through W9 for ID9 5 ID5 5 100 A and VOV 5 0.25 V throughout. (b) Find the voltage gain and the output resistance. (c) Assuming 61.65-V supplies, fi nd the input voltage range and the output voltage swing, as well as the value of VLS that will make vIC(max) 5 VDD.