Figure 26.62 shows an op-amp based on the topology seen in Fig. 26.40 but biased for lower VDD operation. Select the size of the added gate-drain connected MOSFET to allow for proper operation. Simulate the operation of the design showing the DC gain and large signal step responses (as in Fig. 26.34 and 26.35).
Already registered? Login
Not Account? Sign up
Enter your email address to reset your password
Back to Login? Click here