Figure 16.73 shows the addition of I/O (input/output) transistors to the memory array and NSA seen in Fig XXXXXXXXXXSketch a column decoder design using static logic. Show how the 3-bit input address...

Figure 16.73 shows the addition of I/O (input/output) transistors to the memory array and NSA seen in Fig. 16.17. Sketch a column decoder design using static logic. Show how the 3-bit input address is connected to each stage.

109:

Suppose a 2Mbit memory is to be designed as a x²
part (2-bit input/output words). Further suppose that 10 address pins are available to access the memory. Sketch a block diagram of how the row and column addresses are multiplexed together and stored in separate registers. Use
and
, as discussed in the chapter to clock in the addresses. Comment on the validity of using 20-bits to access 2Mbits of data.