Electrical Engineering Question 7 module TEST_gate; reg[8*7:1] str; initial begin str="CMP 2007"; $display ("str= %s",str); end endmodule Which of the following is the output of the above verilog...

Extracted text: Electrical Engineering Question 7 module TEST_gate; reg[8*7:1] str; initial begin str="CMP 2007"; $display ("str= %s",str); end endmodule Which of the following is the output of the above verilog code? Your answer: O str=CMP 2007 O str= MP 2007 O CMP 2007 O MP 2007 Which of the following is the output of the above verilog code?