Electrical Engineering 1.) Consider the following series of address references, given as byte addresses: 4. 16, 32, 20, 80, 68, 76, 224, 36, 44, 16, 172, 20, 24, 36, 68 Label each reference as a hit...

Extracted text: Electrical Engineering 1.) Consider the following series of address references, given as byte addresses: 4. 16, 32, 20, 80, 68, 76, 224, 36, 44, 16, 172, 20, 24, 36, 68 Label each reference as a hit or miss, and show the final cache contents, for each of the following caches. Assume LRU replacement (where appropriate). a.) Direct-mapped, 16x 4-byte blocks. b.) Direct-mapped, 16-byte blocks, total size of 64 bytes. c.) Two-way set associative, 4-byte blocks, total size of 64 bytes. d.) Fully associative, 4-byte blocks, total size of 64 bytes.