Draw the output waveforms f, g and h, given the Verilog module in Figure 1 and inputs specified in Figure 2. Clearly show the timings in your waveforms.

Draw the output waveforms f, g and h, given the Verilog module in Figure 1 and inputs<br>specified in Figure 2. Clearly show the timings in your waveforms.<br>

Extracted text: Draw the output waveforms f, g and h, given the Verilog module in Figure 1 and inputs specified in Figure 2. Clearly show the timings in your waveforms.

module test (clk, a, b, f, g, h);<br>input clk, a, b;<br>output f, g, h;<br>reg f, g, h;<br>always@ (negedge glk)<br>f <= #5<br>a| b;<br>alwayse (clk)<br>g = #10 f ^ b;<br>alwayse (f or g)<br>h = #2 f & g;<br>endmodule<br>Figure 1<br>

Extracted text: module test (clk, a, b, f, g, h); input clk, a, b; output f, g, h; reg f, g, h; always@ (negedge glk) f <= #5="" a|="" b;="" alwayse="" (clk)="" g="#10" f="" ^="" b;="" alwayse="" (f="" or="" g)="" h="#2" f="" &="" g;="" endmodule="" figure="">

Jun 08, 2022

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Draw the output waveforms f, g and h, given the Verilog module in Figure 1 and inputs specified in Figure 2. Clearly show the timings in your waveforms.

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