Draw the block level diagram of the pipelined operand fetch (OF) stage of 5- stage pipeline(IF,OF,EX,MA,RW) – along with the Interlock mechanism. Clearly mention all the signals, clock, and Interface...

Draw the block level diagram of the pipelined operand fetch (OF) stage of 5-

stage pipeline(IF,OF,EX,MA,RW) – along with the Interlock mechanism. Clearly mention all the

signals, clock, and Interface registers (IF-OF and OF-EX). Also write the simplified truth table for