Draw a state diagram and write an HDL model of a Mealy synchronous state machine having a single input x_in and a single output y_out, such that y_out is asserted if the total number of 1’s received...

Draw a state diagram and write an HDL model of a Mealy synchronous state machine having a single input x_in and a single output y_out, such that y_out is asserted if the total number of 1’s received is a multiple of 3.

Develop the state diagram for a Mealy state machine that detects a sequence of three or more consecutive 1’s in a string of bits coming through an input line.