Draw a block diagram for a 4-bit, 1.5-bit-per-stage pipelined converter with error correction. With and , find the residue voltages and , the digital codes at the outputs of each stage, and the final...

Draw a block diagram for a 4-bit, 1.5-bit-per-stage pipelined converter with error correction. With and , find the residue voltages and , the digital codes at the outputs of each stage, and the final digital output after decoding assuming all blocks are ideal. Repeat assuming the upper comparator of stage 1 makes an error.