Do the homework per requirement
Introduction to ISA using SimpleScalar In this exercise, you will run some Benchmarks to find out the distribution of instructions they execute. You will use sim-profile simulator (discussed in the "Introdution to SimpleScalar" webpage) available in the SimpleScalar toolset for this purpose. In the first part of this lab, you will use SimpleScalar configured for ALPHA ISA while in the second part, you will use both ALPHA and PISAconfiguration. If you want to run other benchmarks, they are available at www.simplescalar.com in the Benchmarks section. [Note: Results of simulation may vary over multiple runs and among students in all the labs. This fact is stated at www.simplescalar.com . You should see FAQ section at this website. But the results will be consistent which means they will make sense.] Part 1 Quick fact about sim-profile simulator It is a dynamic instruction profiler which means it collects information about instructions as they are executed by the simulator. Note that it is a functional simulator and not a detailed timing simulator as sim-outorder. All the simulators including sim-profile are available in the home/simplesim-3.0 directory. Go to home/simplesim-3.0 directory and type the following to seek help about sim-profile. home/simplesim-3.0$./sim-profile –h Help can also be invoked just by typing simulator name without any arguments. Go through help. Now use this help information to execute the following four benchmarks available in this tar file. Click benchmarks.tar.gz to download this file. Unzip and Untar this file in a directory e.g. /home/benchmark directory. The information on how to execute these benchmarks using sim-safe is available in the README file which is also in the home/benchmark directory. Replace sim-safe with sim-profile and add information using sim-profile help to fill out the following table 1) anagram: a program for finding anagrams for a phrase, based on a dictionary. 2) compress: (SPEC) compresses and decompresses a file in memory. 3) go: Artificial intelligence; plays the game of go against itself. 4) gcc: (SPEC) limited version of gcc. Benchmark Total # of Instructions Load % Store % Uncond Branch % Cond Branch % Integer Computation % Floating pt Computation % anagram.alpha go.alpha compress.alpha gcc.alpha Now answer the following questions for each individual benchmark executed above 1) Is the benchmark memory intensive or computation intensive? 2) Is the benchmark mainly using integer or floating point computations? 3) What % of the instructions executed are conditional branches? Given this %, how many instructions on average does the processor execute between each pair of conditional branch instructions (do not include the conditional branch instructions) Part 2 In this part, you will compare the PISA and Alpha ISA by executing the same benchmarks on the two configurations. Since the configuration from part 1 is still Alpha, execute the following benchmarks available in the home/simplesim-3.0/tests-alpha/bin/ directory using sim-profile and record the results in the following table. 1) test-math: performs various math computations mostly in integer and displays their result. 2) test-fmath: performs various math functions mostly in integer. 3) test-llong: performs computations in long format. 4) test-printf: displays various print statements. ALPHA Benchmark Total # of instructions Load % Store % Uncond branch % Cond branch % Integer Compute % Floating compute % test-math test-fmath test-llong Test-printf Now change configuration to PISA by typing the following three commands in a sequence. home/simplesim-3.0$./make clean home/simplesim-3.0$./make config-pisa home/simplesim-3.0$./make To change configuration back to Alpha, execute the same command sequence except that in the second command replace config-pisa by config-alpha. Now execute the following benchmarks available in the home/simplesim-3.0/tests-pisa/bin/ directory using sim-profile and record the results in the following table. PISA Benchmark Total # of instructions Load % Store % Uncond branch % Cond branch % Integer Compute % Floating compute % test-math test-fmath test-llong test-printf Now compare the two ISAs using a plot (a Histogram is preferred). Use MATLAB or EXCEL to plot the histogram. What can you conclude about the two ISAs from the Histogram. Simplescalar: an infrastructure for computer system modeling - Computer 0018-9162/02/$17.00 © 2002 IEEE February 2002 59 C O V E R F E A T U R E SimpleScalar: An Infrastructure for Computer System Modeling T o accelerate hardware development, designers often employ software models of the hardware they build. They implement these models in traditional programming languages or hardware description lan- guages, then exercise them with the appropriate workload. Designers can execute programs on these models to validate the performance and cor- rectness of a proposed hardware design. Programmers can use software models to develop and test software before the real hardware becomes available. Although software models are slower than their hardware counterparts, programmers can build and test them in minutes or hours rather than in the months needed to build real hardware. This fast mechanism for design and test provides shorter time to market and much higher quality first silicon. Three critical requirements drive the implemen- tation of a software model: performance, flexibility, and detail. Performance determines the amount of workload the model can exercise given the machine resources available for simulation. Flexibility indi- cates how well the model is structured to simplify modification, permitting design variants or even completely different designs to be modeled with ease. Detail defines the level of abstraction used to implement the model’s components. A highly detailed model will faithfully simulate all aspects of machine operation, whether or not a particular aspect is important to any metric being measured. In practice, optimizing all three model charac- teristics in tandem is difficult. Thus, most model implementations optimize only one or two of them, which explains why so many software models exist, even for a single product design. Research models tend to optimize performance and flexibility at the expense of detail. The SimpleScalar toolset provides an infrastruc- ture for simulation and architectural modeling. The toolset can model a variety of platforms ranging from simple unpipelined processors to detailed dynamically scheduled microarchitectures with multiple-level memory hierarchies. For users with more individual needs, SimpleScalar offers a docu- mented and well-structured design, which simpli- fies extending the toolset to accomplish most architectural modeling tasks. SimpleScalar simulators reproduce computing device operations by executing all program instruc- tions using an interpreter. The toolset’s instruction interpreters support several popular instruction sets, including Alpha, Power PC, x86, and ARM. MODELING BASICS The typical approach to computer system mod- eling leverages a simple approximate model with good simulation performance and a modular code structure. This simulator style suits researchers and instructors well because the simple model focuses on the design’s primary components, leaving out Developed to provide an infrastructure for simulation and architectural modeling, the SimpleScalar toolset offers an open source distribution especially suited to the needs of researchers and instructors. Todd Austin Eric Larson Dan Ernst University of Michigan 60 Computer the minutiae of detail that might otherwise hinder the model’s performance and flexibility. Industrial users, on the other hand, require very detailed mod- els to minimize design risk. Detailed modeling assures that a design has no faulty components or acute performance bottlenecks. The additional detail necessary to implement these models usually comes at the expense of model performance. In industrial applications, individual model performance often takes a backseat because companies have the resources available to stock large simulation server pools. Hardware simulation tends to be a throughput-bound task: Designers want to simulate multiple design configurations run- ning several benchmarks. Adding more machines to the simulation pool decreases the overall runtime to the maximum runtime of any single experiment. For example, Intel’s Pentium 4 design team used a simulation pool that contained more than 1,000 workstations.1 In some cases, designers optimize a model for performance and detail at the expense of flexibility. Designers typically employ these models when they need to faithfully represent a device at speeds capa- ble of executing large workloads, but don’t need to change the model. Software performance analysis is an example of this type of application. Software developers need accurate depictions of program performance, but rarely require changes to the model because they are only concerned with program performance for a particular processor. The FastSIM simulator2 microarchitecture uses memoization to record internal simulator states and the actions taken—such as statistical variable update—upon entering those states. This permits microarchitectural models of arbitrarily high detail to quickly process instructions. However, the imple- mentation sacrifices significant flexibility because the approach requires all microarchitecture com- ponents to provide internal-state hashing mecha- nisms and recording of per-cycle actions. MODELING WITH SIMPLESCALAR SimpleScalar was written in 1992 as part of the Multiscalar project at the University of Wisconsin, under Gurindar Sohi’s direction. In 1995, with Doug Burger’s assistance, the toolset was released as an open source distribution freely available to academic noncommercial users. SimpleScalar LLC now maintains the tool, which is distributed through SimpleScalar’s Web site at http://www. simplescalar.com. Since its release, SimpleScalar has become pop- ular with researchers and instructors in the com- puter architecture research community. For example, in 2000 more than one-third of all papers published in top computer architecture conferences used the SimpleScalar tools to evaluate their designs. SimpleScalar provides an infrastructure for computer system modeling that simplifies implementing hardware models capable of simu- lating complete applications. During simulation, model instrumentation measures the dynamic char- acteristics of the hardware model and the perfor- mance of the software running on it. Figure 1 shows a typical SimpleScalar user ses- sion, with the persistence-of-vision raytracer (POV- ray) graphics application running on a detailed Alpha processor microarchitecture model. The sim- ulated graphical display in the screen’s upper-left corner shows the program I/O. The simulator con- sole window in the screen’s upper-right corner dis- plays simulator-generated messages plus stdout/ stderr, the simulated program’s standard output. At the bottom of the screen, the graphical pipeline view window provides a graphical representation of the simulated program’s execution on the detailed microarchitecture model. GPV shows the execution of instructions from fetch until retirement, displaying each instruction’s state throughout the pipeline. In the example, the blue lines in the display represent long-latency I- cache misses. GPV forms part of SimpleScalar’s visu- alization infrastructure and provides a useful tool for identifying hardware and software bottlenecks.3 SimpleScalar includes several sample models suit- able for a variety of common architectural analy- sis tasks. Table 1 lists the simulator models included with SimpleScalar version 3.0. The simulators range from sim-safe, a minimal SimpleScalar sim- ulator that emulates only the instruction set, to sim- outorder, a detailed microarchitectural model with Figure 1. Sample SimpleScalar user session. (a) The console window dis- plays simulator-gen- erated messages, (b) the graphical pipeline viewer provides a represen- tation of the simu- lated program’s execution, and (c) the simulated graphical display shows program output. (a) (c) (b) February 2002 61 dynamic scheduling, aggressive speculative execu- tion,