Design the CMOS differential pair circuit in Fig. P4.29 to have a differential gain of 3 V/V and a 3-dB bandwidth of 700 MHz when . The transistors should be biased with and should have gate lengths...

Design the CMOS differential pair circuit in Fig. P4.29 to have a differential gain of 3 V/V and a 3-dB bandwidth of 700 MHz when . The transistors should be biased with and should have gate lengths of 0.2 μm. Using the 0.18-μm CMOS parameters in Table 1.5, determine the widths of the transistors and the values of and .