Design a single-digit decade counter that counts from 0 to 9 and repeats. The single-digit decade counter should be built by a cascaded synchronous binary counter (74LS163) and other basic logic...

Design a single-digit decade counter that counts from 0 to 9 and repeats. The single-digit decade counter should be built by a cascaded synchronous binary counter (74LS163) and other basic logic gates. Simulate the complete counter circuit by OrCAD and PSPICE. Capture the circuit schematic and the simulated waveform. (Define the simulation timings for at least one full counting cycle from 0 to 9 and back to 0.) (Hint: Use the DigClock input from the SOURCE as shown below and setup the CLK ONTIME and OFFTIME accordingly for the clock source.)

Extracted text: Part DigClock Part List 1. DCkck FileStimi FileStim16 OFFTIME = .5uS DSTM1 ONTIME = .5us DELAY = STARTVAL = O OPPVAL = 1 CLK FileStim32 FileStim4 FileStime IAC Libraries: abc Design Cache EVAL SOURCE