D Question 20 A processor's memory hierarchy has 3 level caches, followed by the main memory. Below are the miss ratios and latencies experienced by an application: L1 miss ratio = 0.6 %3D L1 hit...

Extracted text: D Question 20 A processor's memory hierarchy has 3 level caches, followed by the main memory. Below are the miss ratios and latencies experienced by an application: L1 miss ratio = 0.6 %3D L1 hit latency = 4 CPI L2 miss ratio = 0.4 L2 hit latency = 10 CPI L3 miss ratio - 0.35 L3 miss latency 300 CPI L3 hit latency 30 CPI What would be the effective processor performance (in terms of CPI) for the application?