Create a detail timing diagram to analyze the hold check timing of the circuit as shown in Figure Q4 below. Assume that a hold violation occurs in the circuit due to the short logic delay between...

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Extracted text: Create a detail timing diagram to analyze the hold check timing of the circuit as shown in Figure Q4 below. Assume that a hold violation occurs in the circuit due to the short logic delay between FF2/Q and FF3/D. Your timing diagram should include signals from CLKA, CLKB, FF2/D, FF2/Q, FF3/D and (b) FF3/Q only. Suggest how this type of violation can be fixed. FF2 FF3 FF1 Q CLK CLKA CLKB Figure Q4