Course: Introduction to Hardware Language (HDL) Topic: while Statement verilog (BCD While if) Create a verilog program for the following condition: if w3=0, display down counter if w3=1, display up...

Course: Introduction to Hardware Language (HDL)

Topic: while Statement verilog (BCD While if)

Create a verilog program for the following condition:

• if w3=0, display down counter


• if w3=1, display up counter


• Please refer to the output of the program together with the source code


• 
  Note: Please use the Source Code that I provided to be able to determine the same result.
  

Extracted text: C:\iverilog\bin>vvp digit_while3 time w3w2w1w0 Y 0000 0111 1 0001 0110 2 3 0010 0101 0011 0100 4 5 0100 0011 0101 0010 0110 0001 7 8 9 10 11 12 13 0111 0000 1000 0001 1001 0010 1010 0011 1011 0100 1100 0101 1101 0110 14 1110 0111 15 1111 1000


Extracted text: module whilel (y,w3,w2,wl,w0); input [3:0]w3,w2,w1,w0; output [3:0]y; 4 5 7 reg [3:0]y; reg [3:0]k; 8. 10 11 always e (w) Ebegin 13 if (w[2]==1'b0) 14 y=4'b0000; 15 else begin y=0;| 16 17 18 k=0; 19 while (k